Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9639652 | Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors | Paul Chang, Jie Deng, Terrence B. Hook, Sim Y. Loo, Jae-Eun Park +2 more | 2017-05-02 |
| 8997028 | Methods and system for analysis and management of parametric yield | James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason D. Hibbeler | 2015-03-31 |
| 8754412 | Intra die variation monitor using through-silicon via | Xiaojun Yu, Toshiaki Kirihata | 2014-06-17 |
| 8626480 | Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors | Paul Chang, Jie Deng, Terrence B. Hook, Sim Y. Loo, Jae-Eun Park +2 more | 2014-01-07 |
| 8429576 | Methods and system for analysis and management of parametric yield | James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason D. Hibbeler | 2013-04-23 |
| 8239790 | Methods and system for analysis and management of parametric yield | James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason D. Hibbeler | 2012-08-07 |
| 8168971 | Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain | Dureseti Chidambarrao, Dan M. Mocuta, Carl Radens | 2012-05-01 |
| 8106462 | Balancing NFET and PFET performance using straining layers | Xiangdong Chen, Weipeng Li, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein +8 more | 2012-01-31 |
| 8042070 | Methods and system for analysis and management of parametric yield | James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason D. Hibbeler | 2011-10-18 |
| 7928513 | Protection against charging damage in hybrid orientation transistors | Terence B. Hook, Jeffrey W. Sleight, Anthony K. Stamper | 2011-04-19 |
| 7879650 | Method of providing protection against charging damage in hybrid orientation transistors | Terence B. Hook, Jeffrey W. Sleight, Anthony K. Stamper | 2011-02-01 |
| 7723750 | MOSFET with super-steep retrograded island | Huilong Zhu, Effendi Leobandung, Dan M. Mocuta | 2010-05-25 |
| 7705345 | High performance strained silicon FinFETs device and method for forming same | Stephen W. Bedell, Kevin K. Chan, Dureseti Chidambarrao, Silke H. Christianson, Jack O. Chu +4 more | 2010-04-27 |
| 7691698 | Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain | Dureseti Chidambarrao, Dan M. Mocuta, Carl Radens | 2010-04-06 |
| 7655557 | CMOS silicide metal gate integration | Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub Kedzierski +6 more | 2010-02-02 |
| 7560326 | Silicon/silcion germaninum/silicon body device with embedded carbon dopant | Dureseti Chidambarrao, Ricardo A. Donaton, David M. Onsongo, Kern Rim | 2009-07-14 |
| 7492016 | Protection against charging damage in hybrid orientation transistors | Terence B. Hook, Jeffrey W. Sleight, Anthony K. Stamper | 2009-02-17 |
| 7411227 | CMOS silicide metal gate integration | Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub Kedzierski +6 more | 2008-08-12 |
| 7268049 | Structure and method for manufacturing MOSFET with super-steep retrograded island | Huilong Zhu, Effendi Leobandung, Dan M. Mocuta | 2007-09-11 |
| 7067400 | Method for preventing sidewall consumption during oxidation of SGOI islands | Stephen W. Bedell | 2006-06-27 |
| 7056782 | CMOS silicide metal gate integration | Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub Kedzierski +6 more | 2006-06-06 |
| 6916698 | High performance CMOS device structure with mid-gap metal gate | Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta, Huajie Chen | 2005-07-12 |
| 6881635 | Strained silicon NMOS devices with embedded source/drain | Dureseti Chidambarrao, Effendi Leobandung, Haining Yang, Huilong Zhu | 2005-04-19 |
| 6762469 | High performance CMOS device structure with mid-gap metal gate | Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta, Huajie Chen | 2004-07-13 |
| 6746924 | Method of forming asymmetric extension mosfet using a drain side spacer | Byoung Hun Lee | 2004-06-08 |