Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9710577 | Heat source integration for electromigration analysis | Steven J. Baumgartner, James M. Johnson | 2017-07-18 |
| 9405311 | Bias-temperature induced damage mitigation circuit | David P. Paulsen, Kirk D. Peterson, John E. Sheets, II | 2016-08-02 |
| 9401643 | Bias-temperature induced damage mitigation circuit | David P. Paulsen, Kirk D. Peterson, John E. Sheets, II | 2016-07-26 |
| 8451021 | Calibrating on-chip resistors via a daisy chain scheme | Benjamin A. Fox, Nathaniel J. Gibbs, Andrew Benson Maki, Trevor Joseph Timpane | 2013-05-28 |
| 8405165 | Field effect transistor having multiple conduction states | Dureseti Chidambarrao, David R. Hanson | 2013-03-26 |
| 8354678 | Structure and method for forming a light detecting diode and a light emitting diode on a silicon-on-insulator wafer backside | Benjamin A. Fox, Nathaniel J. Gibbs, Andrew Benson Maki, Trevor Joseph Timpane | 2013-01-15 |
| 8222702 | CMOS diodes with dual gate conductors, and methods for forming the same | Werner Rausch, Haining Yang | 2012-07-17 |
| 7768041 | Multiple conduction state devices having differently stressed liners | Dureseti Chidambarrao | 2010-08-03 |
| 7737500 | CMOS diodes with dual gate conductors, and methods for forming the same | Werner Rausch, Haining Yang | 2010-06-15 |
| 7560326 | Silicon/silcion germaninum/silicon body device with embedded carbon dopant | Anda C. Mocuta, Dureseti Chidambarrao, Ricardo A. Donaton, Kern Rim | 2009-07-14 |
| 7337420 | Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models | Dureseti Chidambarrao, Donald L. Jordan, Judith H. McCullen, Tina Wagner, Richard Q. Williams | 2008-02-26 |
| 7242239 | Programming and determining state of electrical fuse using field effect transistor having multiple conduction states | David R. Hanson, Dureseti Chidambarrao, Gregory J. Fredeman | 2007-07-10 |
| 7123529 | Sense amplifier including multiple conduction state field effect transistor | David R. Hanson, Dureseti Chidambarrao | 2006-10-17 |