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Integrated circuit performance modeling using a connectivity-based condensed resistance model for a conductive structure in an integrated circuit |
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2018-07-24 |
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Method of determining FET source/drain wire, contact, and diffusion resistances in the presence of multiple contacts |
Lewis W. Dewey, III, Ning Lu, Cole E. Zemke |
2013-07-02 |
| 8302040 |
Compact model methodology for PC landing pad lithographic rounding impact on device performance |
Dureseti Chidambarrao, Gerald M. Davidson, Paul A. Hyde, Shreesh Narasimha |
2012-10-30 |
| 8296691 |
Methodology for improving device performance prediction from effects of active area corner rounding |
Dureseti Chidambarrao, Gerald M. Davidson, Paul A. Hyde, Shreesh Narasimha |
2012-10-23 |
| 7979815 |
Compact model methodology for PC landing pad lithographic rounding impact on device performance |
Dureseti Chidambarrao, Gerald M. Davidson, Paul A. Hyde, Shreesh Narasimha |
2011-07-12 |
| 7503021 |
Integrated circuit diagnosing method, system, and program product |
Matt Boucher, John M. Cohn, Richard Dauphin, Mark E. Masters, Sarah C. Braasch +1 more |
2009-03-10 |
| 7337420 |
Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models |
Dureseti Chidambarrao, Donald L. Jordan, David M. Onsongo, Tina Wagner, Richard Q. Williams |
2008-02-26 |
| 7302376 |
Device modeling for proximity effects |
Eric Adler, Serge Biesemans, Micah Galland, Terence B. Hook, Eric Phipps +1 more |
2007-11-27 |
| 6519752 |
Method of performing parasitic extraction for a multi-fingered transistor |
William C. Bakker, L. William Dewey, III, Peter A. Habitz, Edward W. Seibert, Michael J. Sullivan |
2003-02-11 |
| 6430729 |
Process and system for maintaining 3 sigma process tolerance for parasitic extraction with on-the-fly biasing |
L. William Dewey, III, Peter A. Habitz, Edward W. Seibert |
2002-08-06 |
