ES

Edward W. Seibert

IBM: 7 patents #14,640 of 70,183Top 25%
Overall (All Time): #741,536 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8756554 Identifying parasitic diode(s) in an integrated circuit physical design Douglas W. Kemerer, Lijiang Wang 2014-06-17
8191030 Identifying parasitic diode(s) in an integrated circuit physical design Douglas W. Kemerer, Lijiang Wang 2012-05-29
7490303 Identifying parasitic diode(s) in an integrated circuit physical design Douglas W. Kemerer, Lijiang Wang 2009-02-10
6519752 Method of performing parasitic extraction for a multi-fingered transistor William C. Bakker, L. William Dewey, III, Peter A. Habitz, Judith H. McCullen, Michael J. Sullivan 2003-02-11
6473887 Inclusion of global wires in capacitance extraction L. William Dewey, III, Peter A. Habitz 2002-10-29
6430729 Process and system for maintaining 3 sigma process tolerance for parasitic extraction with on-the-fly biasing L. William Dewey, III, Peter A. Habitz, Judith H. McCullen 2002-08-06
5761080 Method and apparatus for modeling capacitance in an integrated circuit William DeCamp, John J. Ellis-Monaghan, Peter A. Habitz 1998-06-02