Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11657314 | Microwave-to-optical quantum transducers | Chi Xiong, Jason S. Orcutt, Stephen M. Gates, Swetha Kamlapurkar, Abram L. Falk | 2023-05-23 |
| 10707217 | Semiconductor structures with deep trench capacitor and methods of manufacture | Babar A. Khan, Xinhui Wang, Deepal Wehella-Gamage | 2020-07-07 |
| 10037998 | Semiconductor structures with deep trench capacitor and methods of manufacture | Babar A. Khan, Xinhui Wang, Deepal Wehella-Gamage | 2018-07-31 |
| 9679917 | Semiconductor structures with deep trench capacitor and methods of manufacture | Babar A. Khan, Xinhui Wang, Deepal Wehella-Gamage | 2017-06-13 |
| 9653535 | DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods | Nicolas L. Breil, Dong-Hun Kang, Herbert L. Ho, Rishikesh Krishnan | 2017-05-16 |
| 9496329 | DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods | Nicolas L. Breil, Dong-Hun Kang, Herbert L. Ho, Rishikesh Krishnan | 2016-11-15 |
| 9299766 | DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods | Nicolas L. Breil, Dong-Hun Kang, Herbert L. Ho, Rishikesh Krishnan | 2016-03-29 |
| 8349729 | Hybrid bonding interface for 3-dimensional chip integration | Karl W. Barth, Spyridon Galis, Kevin S. Petrarca, Shahab Siddiqui | 2013-01-08 |
| 8227307 | Method for removing threshold voltage adjusting layer with external acid diffusion process | Kuang-Jung Chen, Wu-Song Huang, Wai-Kin Li | 2012-07-24 |
| 8227870 | Method and structure for gate height scaling with high-k/metal gate technology | Michael P. Chudzik, William K. Henson, Yue Liang | 2012-07-24 |
| 8159060 | Hybrid bonding interface for 3-dimensional chip integration | Karl W. Barth, Spyridon Galis, Kevin S. Petrarca, Shahab Siddiqui | 2012-04-17 |
| 8138037 | Method and structure for gate height scaling with high-k/metal gate technology | Michael P. Chudzik, William K. Henson, Yue Liang | 2012-03-20 |
| 7947907 | Electronics structures using a sacrificial multi-layer hardmask scheme | Matthew E. Colburn, Conal E. Murray, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran +2 more | 2011-05-24 |
| 7875511 | CMOS structure including differential channel stressing layer compositions | Liu Yaocheng, Kern Rim | 2011-01-25 |
| 7863123 | Direct contact between high-κ/metal gate and wiring process flow | Huiming Bu, Michael P. Chudzik, Naim Moumen, Hongwen Yan | 2011-01-04 |
| 7791144 | High performance stress-enhance MOSFET and method of manufacture | Dureseti Chidambarrao, William K. Henson, Kern Rim | 2010-09-07 |
| 7709910 | Semiconductor structure for low parasitic gate capacitance | William K. Henson, Paul Chang, Dureseti Chidambarrao, Yaocheng Liu, Shreesh Narasimha +1 more | 2010-05-04 |
| 7691712 | Semiconductor device structures incorporating voids and methods of fabricating such structures | Dureseti Chidambarrao, Jack A. Mandelman | 2010-04-06 |
| 7615418 | High performance stress-enhance MOSFET and method of manufacture | Dureseti Chidambarrao, William K. Henson, Kern Rim | 2009-11-10 |
| 7608489 | High performance stress-enhance MOSFET and method of manufacture | Dureseti Chidambarrao, William K. Henson, Kern Rim | 2009-10-27 |
| 7560326 | Silicon/silcion germaninum/silicon body device with embedded carbon dopant | Anda C. Mocuta, Dureseti Chidambarrao, David M. Onsongo, Kern Rim | 2009-07-14 |
| 7498271 | Nitrogen based plasma process for metal gate MOS device | Rashmi Jha, Siddarth A. Krishnan, Xi Li, Renee T. Mo, Naim Moumen +3 more | 2009-03-03 |
| 7371684 | Process for preparing electronics structures using a sacrificial multilayer hardmask scheme | Matthew E. Colburn, Conal E. Murray, Satyanarayana V. Nitta, Sampath Purushothaman, Sujatha Sankaran +2 more | 2008-05-13 |
| 6844266 | Anisotropic etching of organic-containing insulating layers | Karen Maex, Michael Baklanov, Serge Vanhaelemeersch, Herbert Struyf, Marc Schaekers | 2005-01-18 |
| 6255227 | Etching process of CoSi2 layers | Karen Maex, Rita Verbeeck, Philippe Jansen, Rita Rooyackers, Ludo Deferm +1 more | 2001-07-03 |