Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11217709 | Graphene-semiconductor heterojunction photodetector and method of manufacturing the same | Kyoung-Eun Chang | 2022-01-04 |
| 10996500 | Optical sheet and backlight unit having same | Jee-hong Min, Ki Wook Lee, Tae Jun Lee, Dong Cheol Lee, Se Jin Oh | 2021-05-04 |
| 10243076 | Ternary barristor with schottky junction graphene semiconductor | Chang Hoo Shim, Yun Ji Kim, So Young Kim | 2019-03-26 |
| 10132984 | Optical sheet assembly and backlight unit comprising same | Sung Sik Cho, Dong Cheol Lee, Tae Jun Lee, Hee Jeong Kim, Ki Wook Lee +1 more | 2018-11-20 |
| 10109746 | Graphene transistor and ternary logic device using the same | Yun Ji Kim, So Young Kim | 2018-10-23 |
| 8236686 | Dual metal gates using one metal to alter work function of another metal | Sang Ho Bae, Kisik Choi, Rino Choi, Craig Huffman, Prashant Majhi +3 more | 2012-08-07 |
| 7943453 | CMOS devices with different metals in gate electrodes using spin on low-k material as hard mask | Bernd Kastenmeier, Naim Moumen, Theodorus E. Standaert | 2011-05-17 |
| 7768620 | Method of fabricating liquid crystal display and liquid crystal display fabricated by the same | Jeong Ho Hwang, Ho-Min Kang, Hee-Young Park, Seung-Jun Lee, Sung-teak Choi | 2010-08-03 |
| 7649608 | Driving chip, display device having the same, and method of manufacturing the display device | Mi-Sook Yim, Ho-Min Kang, Won-Gu Cho, Seung-Jun Lee, Hoon-Kee Min +1 more | 2010-01-19 |
| 7548067 | Methods for measuring capacitance | Kin P. Cheung, Dawei Heh, Rino Choi | 2009-06-16 |
| 7160771 | Forming gate oxides having multiple thicknesses | Anthony I. Chou, Michael P. Chudzik, Toshiharu Furukawa, Oleg Gluschenkov, Paul Kirsch +4 more | 2007-01-09 |
| 6891228 | CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture | Heemyong Park, Paul D. Agnello, Dominic J. Schepis, Ghavam G. Shahidi | 2005-05-10 |
| 6828630 | CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture | Heemyong Park, Paul D. Agnello, Dominic J. Schepis, Ghavam G. Shahidi | 2004-12-07 |
| 6800530 | Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors | Bachir Dirahoui, Effendi Leobandung, Tai-chi Su | 2004-10-05 |
| 6746924 | Method of forming asymmetric extension mosfet using a drain side spacer | Anda C. Mocuta | 2004-06-08 |
| 6653698 | Integration of dual workfunction metal gate CMOS devices | Effendi Leobandung, Ghavam G. Shahidi | 2003-11-25 |
| 5863375 | Apparatus and methods for wafer debonding using a liquid jet | Gi-ho Cha | 1999-01-26 |
| 5837610 | Chemical mechanical polishing (CMP) apparatus and CMP method using the same | Joon Hee Lee | 1998-11-17 |
| 5783022 | Apparatus and methods for wafer debonding using a liquid jet | Gi-ho Cha | 1998-07-21 |
| 5735731 | Wafer polishing device | — | 1998-04-07 |
| 5665631 | SOI substrate manufacturing method | Chi-jung Kang, Kyung Wook Lee, Gi-ho Cha | 1997-09-09 |