Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10573526 | Method of charge controlled patterning during reactive ion etching | Sunit S. Mahajan, Richard S. Wise | 2020-02-25 |
| 9496148 | Method of charge controlled patterning during reactive ion etching | Sunit S. Mahajan, Richard S. Wise | 2016-11-15 |
| 9087927 | Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches | Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-Jung Kwon, Paul C. Parries +1 more | 2015-07-21 |
| 8901706 | Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches | Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Oh-Jung Kwon, Paul C. Parries +1 more | 2014-12-02 |
| 7790553 | Methods for forming high performance gates and structures thereof | Huilong Zhu, Xiaomeng Chen, Mahender Kumar, Brian J. Greene, Jay William Strane +1 more | 2010-09-07 |
| 7358130 | Method for monitoring lateral encroachment of spacer process on a CD SEM | Renee T. Mo, Ravikumar Ramachandran, Eric P. Solecky | 2008-04-15 |
| 7105398 | Method for monitoring lateral encroachment of spacer process on a CD SEM | Renee T. Mo, Ravikumar Ramachandran, Eric P. Solecky | 2006-09-12 |
| 6800530 | Triple layer hard mask for gate patterning to fabricate scaled CMOS transistors | Byoung Hun Lee, Effendi Leobandung, Tai-chi Su | 2004-10-05 |
| 6492259 | Process for making a planar integrated circuit interconnect | Daniel C. Edelstein, Robert C. Greenlese, Harris C. Jones | 2002-12-10 |
| 6281583 | Planar integrated circuit interconnect | Daniel C. Edelstein, Robert C. Greenlese, Harris C. Jones | 2001-08-28 |