Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12356711 | Late gate extension | Ruilong Xie, Christopher J. Waskiewicz, Hemanth Jagannathan, Brent A. Anderson | 2025-07-08 |
| 12310090 | CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor | Heng Wu, Ruilong Xie, Su Chen Fan, Hemanth Jagannathan | 2025-05-20 |
| 12268030 | Self-aligned C-shaped vertical field effect transistor | Ruilong Xie, Robert R. Robison, Hemanth Jagannathan | 2025-04-01 |
| 12183740 | Stacked field-effect transistors | Ruilong Xie, Kangguo Cheng, Curtis S. Durfee, Min Gyu Sung, Julien Frougier +1 more | 2024-12-31 |
| 11973125 | Self-aligned uniform bottom spacers for VTFETS | Ruilong Xie, Hemanth Jagannathan, Eric R. Miller | 2024-04-30 |
| 11646373 | Vertical field effect transistor with bottom spacer | Christopher J. Waskiewicz, Ruilong Xie, Hemanth Jagannathan | 2023-05-09 |
| 11615990 | CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor | Heng Wu, Ruilong Xie, Su Chen Fan, Hemanth Jagannathan | 2023-03-28 |
| 11251287 | Self-aligned uniform bottom spacers for VTFETS | Ruilong Xie, Hemanth Jagannathan, Eric R. Miller | 2022-02-15 |
| 11239119 | Replacement bottom spacer for vertical transport field effect transistors | Ruilong Xie, Heng Wu, Hemanth Jagannathan, Lan Yu, Tao Li | 2022-02-01 |
| 11217692 | Vertical field effect transistor with bottom spacer | Christopher J. Waskiewicz, Ruilong Xie, Hemanth Jagannathan | 2022-01-04 |
| 11189532 | Dual width finned semiconductor structure | Yi Song, Eric R. Miller, Fee Li Lie, Richard A. Conti | 2021-11-30 |
| 11043429 | Semiconductor fins with dielectric isolation at fin bottom | Peng Xu, Kangguo Cheng | 2021-06-22 |
| 10892193 | Controlling active fin height of FinFET device | Yi Song, Veeraraghavan S. Baskar, Ekmini Anuja De Silva | 2021-01-12 |
| 10770361 | Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal | Yi Song, Veeraraghavan S. Baskar, Ekmini Anuja De Silva | 2020-09-08 |
| 10672668 | Dual width finned semiconductor structure | Yi Song, Eric R. Miller, Fee Li Lie, Richard A. Conti | 2020-06-02 |
| 10665514 | Controlling active fin height of FinFET device using etch protection layer to prevent recess of isolation layer during gate oxide removal | Yi Song, Veeraraghavan S. Baskar, Ekmini Anuja De Silva | 2020-05-26 |
| 10636709 | Semiconductor fins with dielectric isolation at fin bottom | Peng Xu, Kangguo Cheng | 2020-04-28 |
| 10586700 | Protection of low temperature isolation fill | Michael P. Belyansky, Richard A. Conti, Dechao Guo, Devendra K. Sadana | 2020-03-10 |
| 10535550 | Protection of low temperature isolation fill | Michael P. Belyansky, Richard A. Conti, Dechao Guo, Devendra K. Sadana | 2020-01-14 |
| 9984916 | Uniform dielectric recess depth during fin reveal | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo | 2018-05-29 |
| 9984935 | Uniform dielectric recess depth during fin reveal | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo | 2018-05-29 |
| 9941134 | Uniform dielectric recess depth during fin reveal | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo | 2018-04-10 |
| 9666474 | Uniform dielectric recess depth during fin reveal | Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo | 2017-05-30 |
| 8685809 | Semiconductor structures having improved contact resistance | Bruce B. Doris, Carl Radens, Anthony K. Stamper | 2014-04-01 |
| 8421077 | Replacement gate MOSFET with self-aligned diffusion contact | Sameer H. Jain, Carl Radens, Shahab Siddiqui | 2013-04-16 |