Issued Patents All Time
Showing 1–25 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8926805 | Method and apparatus for electroplating on SOI and bulk semiconductor wafers | Veeraraghavan S. Basker, Eduard A. Cartier, Hariklia Deligianni, Vamsi K. Paruchuri | 2015-01-06 |
| 8785281 | CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials | Tze-Chiang Chen, Meikei Ieong, Mukesh V. Khare, Chun-Yung Sung, Richard S. Wise +2 more | 2014-07-22 |
| 8551313 | Method and apparatus for electroplating on soi and bulk semiconductor wafers | Veeraraghavan S. Basker, Eduard A. Cartier, Hariklia Deligianni, Vamsi K. Paruchuri | 2013-10-08 |
| 8193051 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics | Nestor A. Bojarczuk, Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank +4 more | 2012-06-05 |
| 8158481 | CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials | Tze-Chiang Chen, Meikei Ieong, Mukesh V. Khare, Chun-Yung Sung, Richard S. Wise +2 more | 2012-04-17 |
| 8153514 | Method of forming metal/high-κ gate stacks with high mobility | Wanda Andreoni, Alessandro C. Callegari, Eduard A. Cartier, Alessandro Curioni, Christopher P. D'Emic +9 more | 2012-04-10 |
| 8039331 | Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors | Scott D. Allen, Cyril Cabral, Jr., Kevin K. Dezfulian, Sunfei Fang, Brian J. Greene +6 more | 2011-10-18 |
| 7999323 | Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices | Eduard A. Cartier, Matthew W. Copel, Bruce B. Doris, Young-Hee Kim, Barry P. Linder +3 more | 2011-08-16 |
| 7944006 | Metal gate electrode stabilization by alloying | Veeraraghavan S. Basker, Hariklia Deligianni, Vamsi K. Paruchuri, Lubomyr T. Romankiw | 2011-05-17 |
| 7928514 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics | Nestor A. Bojarczuk, Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank +4 more | 2011-04-19 |
| 7868410 | Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow | Philippe M. Vereecken, Veeraraghavan S. Basker, Cyril Cabral, Jr., Emanuel I. Cooper, Hariklia Deligianni +4 more | 2011-01-11 |
| 7858500 | Low threshold voltage semiconductor device with dual threshold voltage control means | Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni Gousev, Paul C. Jamison +2 more | 2010-12-28 |
| 7785999 | Formation of fully silicided metal gate using dual self-aligned silicide process | Cyril Cabral, Jr., Chester T. Dziobkowski, Sunfei Fang, Evgeni Gousev, Vijay Narayanan +4 more | 2010-08-31 |
| 7750418 | Introduction of metal impurity to change workfunction of conductive electrodes | Michael P. Chudzik, Bruce B. Doris, Supratik Guha, Vijay Narayanan, Vamsi K. Paruchuri +2 more | 2010-07-06 |
| 7745278 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high K dielectrics | Nestor A. Bojarczuk, Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank +4 more | 2010-06-29 |
| 7671421 | CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials | Tze-Chiang Chen, Meikei Ieong, Mukesh V. Khare, Chun-Yung Sung, Richard S. Wise +2 more | 2010-03-02 |
| 7667278 | Metal carbide gate structure and method of fabrication | Cyril Cabral, Jr., Christophe Detavernier, Katherine L. Saenger | 2010-02-23 |
| 7655994 | Low threshold voltage semiconductor device with dual threshold voltage control means | Eduard A. Cartier, Mathew W. Copel, Martin M. Frank, Evgeni Gousev, Paul C. Jamison +2 more | 2010-02-02 |
| 7598545 | Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices | Eduard A. Cartier, Matthew W. Copel, Bruce B. Doris, Young-Hee Kim, Barry P. Linder +3 more | 2009-10-06 |
| 7521346 | Method of forming HfSiN metal for n-FET applications | Alessandro C. Callegari, Martin M. Frank, Dianne L. Lacey, Fenton R. McFeely, Sufi Zafar | 2009-04-21 |
| 7479684 | Field effect transistor including damascene gate with an internal spacer structure | Supratik Guha, Hussein I. Hanafi, Paul M. Solomon | 2009-01-20 |
| 7479683 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics | Nestor A. Bojarczuk, Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank +4 more | 2009-01-20 |
| 7452767 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics | Nestor A. Bojarczuk, Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank +4 more | 2008-11-18 |
| 7446380 | Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOS | Nestor A. Bojarczuk, Michael P. Chudzik, Matthew W. Copel, Supratik Guha, Vijay Narayanan +1 more | 2008-11-04 |
| 7425497 | Introduction of metal impurity to change workfunction of conductive electrodes | Michael P. Chudzik, Bruce B. Doris, Supratik Guha, Vijay Narayanan, Vamsi K. Paruchuri +2 more | 2008-09-16 |