Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8866261 | Self-aligned silicide bottom plate for eDRAM applications by self-diffusing metal in CVD/ALD metal process | Qing Cao, Zhengwen Li, Fei Liu, Zhen Zhang | 2014-10-21 |
| 8679938 | Shallow trench isolation for device including deep trench capacitors | Oleg Gluschenkov, Byeong Y. Kim, Rishikesh Krishnan, Daewon Yang | 2014-03-25 |
| 8629022 | Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same | Dureseti Chidambarrao, Yue Liang, Xiaojun Yu, Jun Yuan | 2014-01-14 |
| 8513085 | Structure and method to improve threshold voltage of MOSFETs including a high k dielectric | Brian J. Greene, Effendi Leobandung, Qingqing Liang, Edward P. Maciejewski, Yanfeng Wang | 2013-08-20 |
| 8445974 | Asymmetric FET including sloped threshold voltage adjusting material layer and method of fabricating same | Dureseti Chidambarrao, Yue Liang, Xiaojun Yu, Jun Yuan | 2013-05-21 |
| 8173531 | Structure and method to improve threshold voltage of MOSFETS including a high K dielectric | Brian J. Greene, Effendi Leobandung, Qingqing Liang, Edward P. Maciejewski, Yanfeng Wang | 2012-05-08 |
| 8039382 | Method for forming self-aligned metal silicide contacts | Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Renee T. Mo, Balasubramanian Pranatharthiharan +1 more | 2011-10-18 |
| 8039331 | Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors | Scott D. Allen, Cyril Cabral, Jr., Kevin K. Dezfulian, Brian J. Greene, Rajarao Jammy +6 more | 2011-10-18 |
| 7999332 | Asymmetric semiconductor devices and method of fabricating | Jun Yuan, Dureseti Chidambarrao, Yue Liang, Haizhou Yin, Xiaojun Yu | 2011-08-16 |
| 7923365 | Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon | Jun Jung Kim, Sang-Jine Park, Min Ho Lee, Thomas W. Dyer, O-Sung Kwon +1 more | 2011-04-12 |
| 7863693 | Forming conductive stud for semiconductive devices | Thomas W. Dyer, Jiang Yan | 2011-01-04 |
| 7816219 | Field effect transistors (FETs) with multiple and/or staircase silicide | Xiangdong Chen, Zhijiong Luo, Haining Yang, Huilong Zhu | 2010-10-19 |
| 7785999 | Formation of fully silicided metal gate using dual self-aligned silicide process | Cyril Cabral, Jr., Chester T. Dziobkowski, Evgeni Gousev, Rajarao Jammy, Vijay Narayanan +4 more | 2010-08-31 |
| 7785950 | Dual stress memory technique method and related structure | Jun Jung Kim, Zhijiong Luo, Hung Y. Ng, Nivo Rovedo, Young Way Teh | 2010-08-31 |
| 7618891 | Method for forming self-aligned metal silicide contacts | Randolph F. Knarr, Mahadevaiyer Krishnan, Christian Lavoie, Renee T. Mo, Balasubramanian Pranatharthiharan +1 more | 2009-11-17 |
| 7598572 | Silicided polysilicon spacer for enhanced contact area | Thomas W. Dyer, Ja-Hum Ku, Yong Meng Lee | 2009-10-06 |
| 7585773 | Non-conformal stress liner for enhanced MOSFET performance | Jun Jung Kim, Thomas W. Dyer | 2009-09-08 |
| 7582516 | CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy | Thomas W. Dyer, Judson R. Holt | 2009-09-01 |
| 7541288 | Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques | Jun Jung Kim, Ja-Hum Ku, Jae-eon Park, Alois Gutmann, O-Sung Kwon +2 more | 2009-06-02 |
| 7517767 | Forming conductive stud for semiconductive devices | Thomas W. Dyer, Jiang Yan | 2009-04-14 |
| 7504309 | Pre-silicide spacer removal | Thomas W. Dyer, Jiang Yan, Jun Jung Kim, Yaocheng Liu, Huilong Zhu | 2009-03-17 |
| 7488660 | Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structure | Thomas W. Dyer | 2009-02-10 |
| 7482215 | Self-aligned dual segment liner and method of manufacturing the same | Thomas W. Dyer, Jiang Yan | 2009-01-27 |
| 7410852 | Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors | Scott D. Allen, Cyril Cabral, Jr., Kevin K. Dezfulian, Brian J. Greene, Rajarao Jammy +6 more | 2008-08-12 |
| 7393746 | Post-silicide spacer removal | Thomas W. Dyer, Jiang Yan, Siddhartha Panda, Yong Meng Lee, Junjung Kim | 2008-07-01 |