Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10229876 | Wiring structures and semiconductor devices | Young Bae Kim, Jong Sam Kim, Jin-Hyeung Park, Jeong Hoon Ahn, Hyeok-Sang Oh +3 more | 2019-03-12 |
| 9716043 | Wiring structure and method of forming the same, and semiconductor device including the wiring structure | Jin-Hyeung Park, Yeon-Joo Kim, In Hwan Kim, Kyoung Pil Park, Jeong Hoon Ahn +3 more | 2017-07-25 |
| 8865486 | Organic light emitting display device and method for fabricating the same | Hee Suk Pang | 2014-10-21 |
| 8742436 | Organic light emitting display device and method for fabricating the same | Hee Suk Pang | 2014-06-03 |
| 8338245 | Integrated circuit system employing stress-engineered spacers | Jae Gon Lee, Jong-ho Yang, Victor Chan | 2012-12-25 |
| 8227308 | Method of fabricating semiconductor integrated circuit device | Ha-Jin Lim, Dong-Suk Shin, Pan-Kwi Park, Tae Gyun Kim | 2012-07-24 |
| 7923365 | Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon | Sang-Jine Park, Min Ho Lee, Thomas W. Dyer, Sunfei Fang, O-Sung Kwon +1 more | 2011-04-12 |
| 7838390 | Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein | Joo-chan Kim, Jae-eon Park, Richard A. Conti, Zhao Lun, Johnny Widodo +2 more | 2010-11-23 |
| 7790622 | Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes | Kyoung-Woo Lee, Ja-Hum Ku, Chong-Kwang Chang, Min-Chul Sun, Jong-ho Yang +1 more | 2010-09-07 |
| 7785950 | Dual stress memory technique method and related structure | Sunfei Fang, Zhijiong Luo, Hung Y. Ng, Nivo Rovedo, Young Way Teh | 2010-08-31 |
| 7612414 | Overlapped stressed liners for improved contacts | Xiangdong Chen, Young-Gun Ko, Jae-Eun Park, Haining Yang | 2009-11-03 |
| 7585773 | Non-conformal stress liner for enhanced MOSFET performance | Sunfei Fang, Thomas W. Dyer | 2009-09-08 |
| 7541288 | Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques | Ja-Hum Ku, Jae-eon Park, Sunfei Fang, Alois Gutmann, O-Sung Kwon +2 more | 2009-06-02 |
| 7504309 | Pre-silicide spacer removal | Thomas W. Dyer, Sunfei Fang, Jiang Yan, Yaocheng Liu, Huilong Zhu | 2009-03-17 |
| 7297584 | Methods of fabricating semiconductor devices having a dual stress liner | Jae-eon Park, Ja-Hum Ku, Dae-Kwon Kang, Young Way Teh | 2007-11-20 |