| 8716081 |
Capacitor top plate over source/drain to form a 1T memory device |
Lee-Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan +2 more |
2014-05-06 |
| 8274115 |
Hybrid orientation substrate with stress layer |
Lee-Wee Teo, Chung Woh Lai, Shyue Seng Tan, Shailendra Mishra, Zhao Lun +2 more |
2012-09-25 |
| 8178417 |
Method of forming shallow trench isolation structures for integrated circuits |
Shailendra Mishra, James Yong Meng Lee, Zhao Lun, Wen Zhi Gao, Chung Woh Lai +2 more |
2012-05-15 |
| 8143651 |
Nested and isolated transistors with reduced impedance difference |
Liang-Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun, Huang Liu +5 more |
2012-03-27 |
| 8053327 |
Method of manufacture of an integrated circuit system with self-aligned isolation structures |
Shailendra Mishra, Lee-Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai +2 more |
2011-11-08 |
| 7999300 |
Memory cell structure and method for fabrication thereof |
Zhao Lun, James Yong Meng Lee, Lee-Wee Teo, Shyue Seng Tan, Chung Woh Lai +2 more |
2011-08-16 |
| 7932178 |
Integrated circuit having a plurality of MOSFET devices |
Lee-Wee Teo, Yong Meng Lee, Jeffrey Chee, Shyue Seng Tan, Chung Woh Lai +2 more |
2011-04-26 |
| 7923365 |
Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon |
Jun Jung Kim, Sang-Jine Park, Min Ho Lee, Thomas W. Dyer, Sunfei Fang +1 more |
2011-04-12 |
| 7906426 |
Method of controlled low-k via etch for Cu interconnections |
Wuping Liu, Teck Jung Tang, Jing Hui Li, Han Wah Ng, Larry Clevenger +1 more |
2011-03-15 |
| 7847402 |
BEOL interconnect structures with improved resistance to stress |
Darryl D. Restaino, Griselda Bonilla, Christos D. Dimitrakopoulos, Stephen M. Gates, Jae Hak Kim +4 more |
2010-12-07 |
| 7838390 |
Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein |
Jun Jung Kim, Joo-chan Kim, Jae-eon Park, Richard A. Conti, Zhao Lun +2 more |
2010-11-23 |
| 7829422 |
Integrated circuit having ultralow-K dielectric layer |
Huang Liu, Sin Leng Lim |
2010-11-09 |
| 7795680 |
Integrated circuit system employing selective epitaxial growth technology |
Huang Liu, Alex See, James Yong Meng Lee, Chung Woh Lai, Wenzhi Gao +3 more |
2010-09-14 |
| 7767577 |
Nested and isolated transistors with reduced impedance difference |
Liang-Choo Hsia, James Yong Meng Lee, Wen Zhi Gao, Zhao Lun, Huang Liu +5 more |
2010-08-03 |
| 7737029 |
Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby |
Jae Hak Kim, Griselda Bonilla, Steven E. Molis, Darryl D. Restaino, Hosadurga Shobha |
2010-06-15 |
| 7687381 |
Method of forming electrical interconnects within insulating layers that form consecutive sidewalls including forming a reaction layer on the inner sidewall |
Jae Hak Kim, Jing Hui Li, Wu Ping Liu |
2010-03-30 |
| 7622403 |
Semiconductor processing system with ultra low-K dielectric |
Yasri Yudhistira, Bei Chao Zhang, Liang-Choo Hsia |
2009-11-24 |
| 7566656 |
Method and apparatus for providing void structures |
Huang Liu, Wei Lu |
2009-07-28 |
| 7541288 |
Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques |
Jun Jung Kim, Ja-Hum Ku, Jae-eon Park, Sunfei Fang, Alois Gutmann +2 more |
2009-06-02 |
| 7524755 |
Entire encapsulation of Cu interconnects using self-aligned CuSiN film |
Bei Chao Zhang, Tong Qing Chen, Yong Kong Siew, Fan Zhang, San Leong Liew +2 more |
2009-04-28 |
| 7459388 |
Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stresses |
Jaehak Kim, Darryl D. Restaino |
2008-12-02 |
