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USPTO Patent Rankings Data through Dec 31, 2025
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Larry Clevenger — 14 Patents

IBM: 14 patents #8,031 of 70,183Top 15%
Infineon Technologies Ag: 10 patents #917 of 7,486Top 15%
GPGlobalfoundries Singapore Pte.: 1 patents #427 of 828Top 55%
UMUnited Microelectronics: 1 patents #2,686 of 4,560Top 60%
Lagrangeville, NY: #40 of 200 inventorsTop 20%
New York: #10,566 of 115,490 inventorsTop 10%
Overall (All Time): #332,869 of 4,157,543Top 9%
14 Patents All Time
Larry Clevenger has been granted 14 US patents while listed as an inventor at IBM. The first was granted in 2000 and the most recent in July 2012. Larry Clevenger ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list Larry Clevenger in Lagrangeville, NY, US.

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8232211 Methods for self-aligned self-assembled patterning enhancement Timothy J. Dalton, Carl Radens 2012-07-31 $5,473,000
7906426 Method of controlled low-k via etch for Cu interconnections Wuping Liu, Johnny Widodo, Teck Jung Tang, Jing Hui Li, Han Wah Ng +1 more 2011-03-15 $6,222,000
7365001 Interconnect structures and methods of making thereof Chih-Chao Yang, Louis L. Hsu, Keith Kwong Hon Wong, Timothy J. Dalton, Carl Radens 2008-04-29 $12,832,000
7241696 Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Kaushik A. Kumar, Douglas C. La Tulipe, Jr. +5 more 2007-07-10
7125792 Dual damascene structure and method Kaushik A. Kumar, Douglas C. La Tulipe, Jr., Timothy J. Dalton, Andy Cowley, Erdem Kaltalioglu +1 more 2006-10-24
7091612 Dual damascene structure and method Kaushik A. Kumar, Timothy J. Dalton, Andy Cowley, Douglas C. La Tulipe, Jr., Mark Hoinkis +5 more 2006-08-15
6890815 Reduced cap layer erosion for borderless contacts Johnathan E. Faltermeier, Jeremy K. Stephens, David M. Dobuzinsky, Munir D. Naeem, Chienfan Yu +3 more 2005-05-10
6784105 Simultaneous native oxide removal and metal neutral deposition method Chih-Chao Yang, Yun-Yu Wang, Andrew H. Simon, Stephen E. Greco, Kaushik Chanda +3 more 2004-08-31
6661097 Ti liner for copper interconnect with low-k dielectric Stanley J. Klepeis, Hsiao-Ling Lu, Jeffrey R. Marino, Andrew H. Simon, Yun-Yu Wang +2 more 2003-12-09 $6,520,000
6420216 Fuse processing using dielectric planarization pillars Louis L. Hsu, Chandrasekhar Narayan, Jeremy K. Stephens, Michael Wise 2002-07-16
6361880 CVD/PVD/CVD/PVD fill process Roy Iggulden, Rainer Florian Schnabel, Stefan Weber 2002-03-26
6281114 Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication Chenting Lin, Ranier Florian Schnabel 2001-08-28
6136709 Metal line deposition process Sven Schmidbauer, Stefan Weber, Peter Weigand, Roy Iggulden 2000-10-24
6057236 CVD/PVD method of filling structures using discontinuous CVD AL liner Mark Hoinkis, Roy Iggulden, Stefan Weber 2000-05-02 $31,039,000