LC

Larry Clevenger

IBM: 14 patents #8,004 of 70,183Top 15%
Infineon Technologies Ag: 10 patents #1,452 of 7,486Top 20%
GP Globalfoundries Singapore Pte.: 1 patents #427 of 828Top 55%
UM United Microelectronics: 1 patents #2,686 of 4,560Top 60%
Overall (All Time): #353,722 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8232211 Methods for self-aligned self-assembled patterning enhancement Timothy J. Dalton, Carl Radens 2012-07-31
7906426 Method of controlled low-k via etch for Cu interconnections Wuping Liu, Johnny Widodo, Teck Jung Tang, Jing Hui Li, Han Wah Ng +1 more 2011-03-15
7365001 Interconnect structures and methods of making thereof Chih-Chao Yang, Louis L. Hsu, Keith Kwong Hon Wong, Timothy J. Dalton, Carl Radens 2008-04-29
7241696 Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer Timothy J. Dalton, Mark Hoinkis, Steffen K. Kaldor, Kaushik A. Kumar, Douglas C. La Tulipe, Jr. +5 more 2007-07-10
7125792 Dual damascene structure and method Kaushik A. Kumar, Douglas C. La Tulipe, Jr., Timothy J. Dalton, Andy Cowley, Erdem Kaltalioglu +1 more 2006-10-24
7091612 Dual damascene structure and method Kaushik A. Kumar, Timothy J. Dalton, Andy Cowley, Douglas C. La Tulipe, Jr., Mark Hoinkis +5 more 2006-08-15
6890815 Reduced cap layer erosion for borderless contacts Johnathan E. Faltermeier, Jeremy K. Stephens, David M. Dobuzinsky, Munir D. Naeem, Chienfan Yu +3 more 2005-05-10
6784105 Simultaneous native oxide removal and metal neutral deposition method Chih-Chao Yang, Yun-Yu Wang, Andrew H. Simon, Stephen E. Greco, Kaushik Chanda +3 more 2004-08-31
6661097 Ti liner for copper interconnect with low-k dielectric Stanley J. Klepeis, Hsiao-Ling Lu, Jeffrey R. Marino, Andrew H. Simon, Yun-Yu Wang +2 more 2003-12-09
6420216 Fuse processing using dielectric planarization pillars Louis L. Hsu, Chandrasekhar Narayan, Jeremy K. Stephens, Michael Wise 2002-07-16
6361880 CVD/PVD/CVD/PVD fill process Roy Iggulden, Rainer Florian Schnabel, Stefan Weber 2002-03-26
6281114 Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication Chenting Lin, Ranier Florian Schnabel 2001-08-28
6136709 Metal line deposition process Sven Schmidbauer, Stefan Weber, Peter Weigand, Roy Iggulden 2000-10-24
6057236 CVD/PVD method of filling structures using discontinuous CVD AL liner Mark Hoinkis, Roy Iggulden, Stefan Weber 2000-05-02