RI

Roy Iggulden

IBM: 21 patents #5,175 of 70,183Top 8%
Infineon Technologies Ag: 8 patents #2,021 of 7,486Top 30%
Overall (All Time): #197,538 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8465657 Post chemical mechanical polishing etch for improved time dependent dielectric breakdown reliability Kaushik Chanda, James J. Demarest, Ronald G. Filippi, Edward W. Kiewara, Ping-Chuan Wang +1 more 2013-06-18
7560375 Gas dielectric structure forming methods Ronald G. Filippi, Edward W. Kiewra, Ping-Chuan Wang 2009-07-14
7473636 Method to improve time dependent dielectric breakdown Kaushik Chanda, James J. Demarest, Ronald G. Filippi, Edward W. Kiewra, Vincent J. McGahay +2 more 2009-01-06
7361584 Detection of residual liner materials after polishing in damascene process Ronald G. Filippi, Edward W. Kiewra, Stephen K. Loh, Ping-Chuan Wang 2008-04-22
7287325 Method of forming interconnect structure or interconnect and via structures using post chemical mechanical polishing Kaushik Chanda, James J. Demarest, Ronald G. Filippi, Edward W. Kiewra, Ping-Chuan Wang +1 more 2007-10-30
7119545 Capacitive monitors for detecting metal extrusion during electromigration Ishtiaq Ahsan, Ronald G. Filippi, Edward W. Kiewra, Ping-Chuan Wang 2006-10-10
6960306 Low Cu percentages for reducing shorts in AlCu lines Padraic Shafer, Kwong Hon Wong, Michael Iwatake, Jay William Strane, Thomas Goebel +4 more 2005-11-01
6887785 Etching openings of different depths using a single mask layer method and structure David M. Dobuzinsky, Carl Radens, Jay William Strane, Keith Kwong Hon Wong 2005-05-03
6870263 Device interconnection Lawrence A. Clevenger, Ronald G. Filippi, Mark Hoinkis, Jeffery L. Hurd, Herbert Palm +5 more 2005-03-22
6734097 Liner with poor step coverage to improve contact resistance in W contacts Padraic Shafer, Werner Robl, Kwong Hon Wong 2004-05-11
6635564 Semiconductor structure and method of fabrication including forming aluminum columns Stefan Weber 2003-10-21
6448173 Aluminum-based metallization exhibiting reduced electromigration and method therefor Lawrence A. Clevenger, Ronald G. Filippi, Kenneth P. Rodbell, Chao-Kun Hu, Lynne M. Gignac +3 more 2002-09-10
6444565 Dual-rie structure for via/line interconnections Christopher Adam Feild, Rajiv V. Joshi, Edward W. Kiewra 2002-09-03
6433436 Dual-RIE structure for via/line interconnections Christopher Adam Feild, Rajiv V. Joshi, Edward W. Kiewra 2002-08-13
6413866 Method of forming a solute-enriched layer in a substrate surface and article formed thereby Horatio S. Wildman, Lawrence A. Clevenger, Chenting Lin, Kenneth P. Rodbell, Stefan Weber +2 more 2002-07-02
6383920 Process of enclosing via for improved reliability in dual damascene interconnects Ping-Chuan Wang, Ronald G. Filippi, Robert D. Edwards, Edward W. Kiewra 2002-05-07
6361880 CVD/PVD/CVD/PVD fill process Larry Clevenger, Rainer Florian Schnabel, Stefan Weber 2002-03-26
6252292 Vertical electrical cavity-fuse Axel Brintzinger, Stefan Weber, Peter Weigand 2001-06-26
6242789 Vertical fuse and method of fabrication Stefan Weber, Axel Brintzinger, Mark Hoinkis, Chandrasekhar Narayan, Robert Willem Van Den Berg 2001-06-05
6218279 Vertical fuse and method of fabrication Stefan Weber, Axel Brintzinger, Mark Hoinkis, Chandrasekhar Narayan, Robert Willem Van Den Berg 2001-04-17
6136709 Metal line deposition process Sven Schmidbauer, Stefan Weber, Peter Weigand, Larry Clevenger 2000-10-24
6057236 CVD/PVD method of filling structures using discontinuous CVD AL liner Larry Clevenger, Mark Hoinkis, Stefan Weber 2000-05-02