Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9702930 | Semiconductor wafer probing system including pressure sensing and control unit | Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin | 2017-07-11 |
| 9673089 | Interconnect structure with enhanced reliability | Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Andrew H. Simon, Ping-Chuan Wang | 2017-06-06 |
| 9354252 | Pressure sensing and control for semiconductor wafer probing | Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin | 2016-05-31 |
| 9059111 | Reliable back-side-metal structure | Jeffrey P. Gambino, Charles F. Musante, Ping-Chuan Wang | 2015-06-16 |
| 8963567 | Pressure sensing and control for semiconductor wafer probing | Oleg Gluschenkov, Louis V. Medina, Tso-Hui Ting, Ping-Chuan Wang, Yongchun Xin | 2015-02-24 |
| 8912658 | Interconnect structure with enhanced reliability | Ronald G. Filippi, Ping-Chuan Wang, Griselda Bonilla, Kaushik Chanda, Andrew H. Simon | 2014-12-16 |
| 8053257 | Method for prediction of premature dielectric breakdown in a semiconductor | Kaushik Chanda, Hazara S. Rathore, Paul S. McLaughlin, Lawrence A. Clevenger, Andrew P. Cowley +2 more | 2011-11-08 |
| 7919834 | Edge seal for thru-silicon-via technology | Robert Edgar Davis, J. Edwin Hostetter, Ping-Chuan Wang, Kimball M. Watson | 2011-04-05 |
| 7602265 | Apparatus for accurate and efficient quality and reliability evaluation of micro electromechanical systems | Hariklia Deligianni, Thomas J. Fleischman, Robert A. Groves, Charles J. Montrose, Richard P. Volant +1 more | 2009-10-13 |
| 6383920 | Process of enclosing via for improved reliability in dual damascene interconnects | Ping-Chuan Wang, Ronald G. Filippi, Edward W. Kiewra, Roy Iggulden | 2002-05-07 |
| 5760595 | High temperature electromigration stress test system, test socket, and use thereof | Du Nguyen, James J. Poulin, Hazara S. Rathore, Richard G. Smith | 1998-06-02 |