Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8466056 | Method of forming metal interconnect structures in ultra low-k dielectrics | Birendra Agarwala, Hazara S. Rathore | 2013-06-18 |
| 7692439 | Structure for modeling stress-induced degradation of conductive interconnects | Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi +7 more | 2010-04-06 |
| 7639032 | Structure for monitoring stress-induced degradation of conductive interconnects | Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi +7 more | 2009-12-29 |
| 7397260 | Structure and method for monitoring stress-induced degradation of conductive interconnects | Kaushik Chanda, Birendra Agarwala, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi +7 more | 2008-07-08 |
| 7279411 | Process for forming a redundant structure | Birendra Agarwala, Hazara S. Rathore | 2007-10-09 |
| 7163883 | Edge seal for a semiconductor device | Birendra Agarwala, Hormazdyar M. Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Richard W. Procter +3 more | 2007-01-16 |
| 7138714 | Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines | Birendra Agarwala, Conrad A. Barile, Jawahar P. Nayak, Hazara S. Rathore | 2006-11-21 |
| 6972209 | Stacked via-stud with improved reliability in copper metallurgy | Birendra Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engle, Michael Lane +8 more | 2005-12-06 |
| 6825561 | Structure and method for eliminating time dependent dielectric breakdown failure of low-k material | Birendra Agarwala, Hazara S. Rathore | 2004-11-30 |
| 6734090 | Method of making an edge seal for a semiconductor device | Birendra Agarwala, Hormazdyar M. Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Richard W. Procter +3 more | 2004-05-11 |
| 6348731 | Copper interconnections with enhanced electromigration resistance and reduced defect sensitivity and method of forming same | Leon Ashley, Hormazdyar M. Dalal, Hazara S. Rathore, Richard G. Smith | 2002-02-19 |
| 6294835 | Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof | Hormazdyar M. Dalal, Hazara S. Rathore | 2001-09-25 |
| 6287954 | Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity | Leon Ashley, Hormazdyar M. Dalal, Hazara S. Rathore, Richard G. Smith | 2001-09-11 |
| 6258710 | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity | Hazara S. Rathore, Hormazdyar M. Dalal, Paul S. McLaughlin, Richard G. Smith, Alexander J. Swinton +1 more | 2001-07-10 |
| 6133139 | Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof | Hormazdyar M. Dalal, Hazara S. Rathore | 2000-10-17 |
| 6130161 | Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity | Leon Ashley, Hormazdyar M. Dalal, Hazara S. Rathore, Richard G. Smith | 2000-10-10 |
| 6069051 | Method of producing planar metal-to-metal capacitor for use in integrated circuits | Hazara S. Rathore, George S. Prokop, Richard A. Wachnik, Craig R. Gruszecki | 2000-05-30 |
| 6069068 | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity | Hazara S. Rathore, Hormazdyar M. Dalal, Paul S. McLaughlin, Richard G. Smith, Alexander J. Swinton +1 more | 2000-05-30 |
| 6033939 | Method for providing electrically fusible links in copper interconnection | Birendra Agarwala, Hormazdyar M. Dalal, Hazara S. Rathore | 2000-03-07 |
| 5981374 | Sub-half-micron multi-level interconnection structure and process thereof | Hormazdyar M. Dalal, Hazara S. Rathore | 1999-11-09 |
| 5760595 | High temperature electromigration stress test system, test socket, and use thereof | Robert D. Edwards, James J. Poulin, Hazara S. Rathore, Richard G. Smith | 1998-06-02 |
| 5252516 | Method for producing interlevel stud vias | Hazara S. Rathore | 1993-10-12 |