EL

Eric G. Liniger

IBM: 29 patents #3,528 of 70,183Top 6%
SO Sony: 2 patents #12,963 of 25,231Top 55%
AS Adeia Semiconductor Solutions: 1 patents #22 of 57Top 40%
TE Tessera: 1 patents #207 of 271Top 80%
Overall (All Time): #115,152 of 4,157,543Top 3%
31
Patents All Time

Issued Patents All Time

Showing 25 most recent of 31 patents

Patent #TitleCo-InventorsDate
12224203 Air gap spacer formation for nano-scale semiconductor devices Kangguo Cheng, Thomas J. Haigh, Jr., Juntao Li, Sanjay C. Mehta, Son V. Nguyen +2 more 2025-02-11
11658062 Air gap spacer formation for nano-scale semiconductor devices Kangguo Cheng, Thomas J. Haigh, Jr., Juntao Li, Sanjay C. Mehta, Son V. Nguyen +2 more 2023-05-23
10418277 Air gap spacer formation for nano-scale semiconductor devices Kangguo Cheng, Thomas J. Haigh, Jr., Juntao Li, Sanjay C. Mehta, Son V. Nguyen +2 more 2019-09-17
10309884 Predicting semiconductor package warpage Stephen P. Ayotte, Travis S. Longenbach 2019-06-04
10115629 Air gap spacer formation for nano-scale semiconductor devices Kangguo Cheng, Thomas J. Haigh, Jr., Juntao Li, Sanjay C. Mehta, Son V. Nguyen +2 more 2018-10-30
9892961 Air gap spacer formation for nano-scale semiconductor devices Kangguo Cheng, Thomas J. Haigh, Jr., Juntao Li, Sanjay C. Mehta, Son V. Nguyen +2 more 2018-02-13
9772268 Predicting semiconductor package warpage Stephen P. Ayotte, Travis S. Longenbach 2017-09-26
9613900 Nanoscale interconnect structure Chih-Chao Yang, Stephan A. Cohen 2017-04-04
9281211 Nanoscale interconnect structure Chih-Chao Yang, Stephan A. Cohen 2016-03-08
9018089 Multiple step anneal method and semiconductor formed by multiple step anneal Griselda Bonilla, Pak Leung, Stephen A. Cohen, Stephen M. Gates, Thomas M. Shaw 2015-04-28
7998880 Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties Son V. Nguyen, Sarah L. Lane, Kensaku Ida, Darryl D. Restaino 2011-08-16
7678673 Strengthening of a structure by infiltration Elbert E. Huang, William Francis Landers, Michael Lane, Xiao Hu Liu, David L. Questad +1 more 2010-03-16
7573130 Crack trapping and arrest in thin film structures Thomas M. Shaw, Michael Lane, Xio Hu Liu, Griselda Bonilla, James P. Doyle +1 more 2009-08-11
7517790 Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification John A. Fitzsimmons, Stephen M. Gates, Michael Lane 2009-04-14
7491578 Method of forming crack trapping and arrest in thin film structures Thomas M. Shaw, Michael Lane, Xio Hu Liu, Griselda Bonilla, James P. Doyle +1 more 2009-02-17
7357977 Ultralow dielectric constant layer with controlled biaxial stress Christos D. Dimitrakopoulos, Stephen M. Gates, Alfred Grill, Michael Lane, Xiao Hu Liu +3 more 2008-04-15
7265437 Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical properties Son V. Nguyen, Sarah L. Lane, Kensaku Ida, Darryl D. Restaino 2007-09-04
7247946 On-chip Cu interconnection using 1 to 5 nm thick metal cap John Bruley, Roy A. Carruthers, Lynne M. Gignac, Chao-Kun Hu, Sandra G. Malhotra +1 more 2007-07-24
7163883 Edge seal for a semiconductor device Birendra Agarwala, Hormazdyar M. Dalal, Diana Llera-Hurlburt, Du Nguyen, Richard W. Procter +3 more 2007-01-16
6915795 Method and system for dicing wafers, and semiconductor structures incorporating the products thereof Donald W. Brouillette, Robert F. Cook, Thomas G. Ference, Wayne J. Howell, Ronald L. Mendelson 2005-07-12
6734090 Method of making an edge seal for a semiconductor device Birendra Agarwala, Hormazdyar M. Dalal, Diana Llera-Hurlburt, Du Nguyen, Richard W. Procter +3 more 2004-05-11
6636290 Methods of forming liquid display panels and the like wherein using two-component epoxy sealant James H. Glownia, Gareth G. Hougham, Robert J. von Gutfeld 2003-10-21
6600213 Semiconductor structure and package including a chip having chamfered edges Donald W. Brouillette, Robert F. Cook, Thomas G. Ference, Wayne J. Howell, Ronald L. Mendelson 2003-07-29
6455443 Method of fabricating low-dielectric constant interlevel dielectric films for BEOL interconnects with enhanced adhesion and low-defect density Andrew Robert Eckert, John C. Hay, Jr., Jeffrey Hedrick, Kang-Wook Lee, Eva E. Simonyi 2002-09-24
6271102 Method and system for dicing wafers, and semiconductor structures incorporating the products thereof Donald W. Brouillette, Robert F. Cook, Thomas G. Ference, Wayne J. Howell, Ronald L. Mendelson 2001-08-07