| 8466056 |
Method of forming metal interconnect structures in ultra low-k dielectrics |
Du Nguyen, Hazara S. Rathore |
2013-06-18 |
| 7692439 |
Structure for modeling stress-induced degradation of conductive interconnects |
Kaushik Chanda, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi, Jason P. Gill +7 more |
2010-04-06 |
| 7639032 |
Structure for monitoring stress-induced degradation of conductive interconnects |
Kaushik Chanda, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi, Jason P. Gill +7 more |
2009-12-29 |
| 7470613 |
Dual damascene multi-level metallization |
Eric M. Coker, Anthony Correale, Jr., Hazara S. Rathore, Timothy D. Sullivan, Richard A. Wachnik |
2008-12-30 |
| 7397260 |
Structure and method for monitoring stress-induced degradation of conductive interconnects |
Kaushik Chanda, Lawrence A. Clevenger, Andrew P. Cowley, Ronald G. Filippi, Jason P. Gill +7 more |
2008-07-08 |
| 7279411 |
Process for forming a redundant structure |
Du Nguyen, Hazara S. Rathore |
2007-10-09 |
| 7224063 |
Dual-damascene metallization interconnection |
Eric M. Coker, Anthony Correale, Jr., Hazara S. Rathore, Timothy D. Sullivan, Richard A. Wachnik |
2007-05-29 |
| 7163883 |
Edge seal for a semiconductor device |
Hormazdyar M. Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Nguyen, Richard W. Procter +3 more |
2007-01-16 |
| 7138714 |
Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines |
Du Nguyen, Conrad A. Barile, Jawahar P. Nayak, Hazara S. Rathore |
2006-11-21 |
| 6972209 |
Stacked via-stud with improved reliability in copper metallurgy |
Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engle, Michael Lane, Ernest N. Levine +8 more |
2005-12-06 |
| 6825561 |
Structure and method for eliminating time dependent dielectric breakdown failure of low-k material |
Du Nguyen, Hazara S. Rathore |
2004-11-30 |
| 6734090 |
Method of making an edge seal for a semiconductor device |
Hormazdyar M. Dalal, Eric G. Liniger, Diana Llera-Hurlburt, Du Nguyen, Richard W. Procter +3 more |
2004-05-11 |
| 6271599 |
Wire interconnect structure for electrically and mechanically connecting an integrated circuit chip to a substrate |
William H. Ma |
2001-08-07 |
| 6111321 |
Ball limiting metalization process for interconnection |
— |
2000-08-29 |
| 6033939 |
Method for providing electrically fusible links in copper interconnection |
Hormazdyar M. Dalal, Du Nguyen, Hazara S. Rathore |
2000-03-07 |
| 5376584 |
Process of making pad structure for solder ball limiting metallurgy having reduced edge stress |
— |
1994-12-27 |
| 5268072 |
Etching processes for avoiding edge stress in semiconductor chip solder bumps |
Madhav Datta, Richard E. Gegenwarth, Christopher V. Jahnes, Patrick M. Miller, Henry A. Nye, III +2 more |
1993-12-07 |
| 5251806 |
Method of forming dual height solder interconnections |
Aziz Mohammad Ahsan, Arthur Bross, Mark F. Chadurjian, Nicholas G. Koopman, Li-Chung Lee +8 more |
1993-10-12 |
| 5130779 |
Solder mass having conductive encapsulating arrangement |
Aziz Mohammad Ahsan, Arthur Bross, Mark F. Chadurjian, Nicholas G. Koopman, Li-Chung Lee +8 more |
1992-07-14 |
| 4985310 |
Multilayered metallurgical structure for an electronic component |
Keith F. Beckman, Alice H. Cooper-Joselow, Chandrasekhar Narayan, Sampath Purushothaman, Sudipta K. Ray |
1991-01-15 |
| 4970570 |
Use of tapered head pin design to improve the stress distribution in the braze joint |
Paul H. Palmateer, Da-Yuan Shih |
1990-11-13 |
