Issued Patents All Time
Showing 25 most recent of 113 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11980111 | Confined bridge cell phase change memory | Injo Ok, Kevin W. Brew, Muthumanickam Sankarapandian, Steven Michael McDermott, Nicole Saulnier | 2024-05-07 |
| 11930724 | Phase change memory cell spacer | Injo Ok, Nicole Saulnier, Muthumanickam Sankarapandian, Steven Michael McDermott, Iqbal Rashid Saraf | 2024-03-12 |
| 11476418 | Phase change memory cell with a projection liner | Injo Ok, Ruqiang Bao, Kevin W. Brew, Nicole Saulnier, Iqbal Rashid Saraf +1 more | 2022-10-18 |
| 11456415 | Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner | Injo Ok, Ruqiang Bao, Kevin W. Brew, Nicole Saulnier, Iqbal Rashid Saraf +2 more | 2022-09-27 |
| 10256186 | Interconnect structure having subtractive etch feature and damascene feature | Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Elbert E. Huang, Naftali E. Lustig | 2019-04-09 |
| 10229875 | Stacked via structure for metal fuse applications | Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig +1 more | 2019-03-12 |
| 10224236 | Forming air gap | Samuel S. Choi, Ronald G. Filippi, Elbert E. Huang, Naftali E. Lustig, Griselda Bonilla | 2019-03-05 |
| 10177091 | Interconnect structure and method of forming | Chih-Chao Yang | 2019-01-08 |
| 10177031 | Subtractive etch interconnects | Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig | 2019-01-08 |
| 10103068 | Detecting a void between a via and a wiring line | Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Elbert E. Huang, Naftali E. Lustig | 2018-10-16 |
| 10079175 | Insulating a via in a semiconductor substrate | Mukta G. Farooq, Jennifer A. Oakley, Kevin S. Petrarca, Nicole R. Reardon | 2018-09-18 |
| 9893011 | Back-end electrically programmable fuse | Junjing Bao, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi +3 more | 2018-02-13 |
| 9852980 | Interconnect structure having substractive etch feature and damascene feature | Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Elbert E. Huang, Naftali E. Lustig | 2017-12-26 |
| 9793216 | Fabrication of IC structure with metal plug | Joyeeta Nag, Jim Shih-Chun Liang, Domingo A. Ferrer Luppi, Atsushi Ogino, Michael P. Chudzik | 2017-10-17 |
| 9728450 | Insulating a via in a semiconductor substrate | Mukta G. Farooq, Jennifer A. Oakley, Kevin S. Petrarca, Nicole R. Reardon | 2017-08-08 |
| 9685404 | Back-end electrically programmable fuse | Junjing Bao, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi +3 more | 2017-06-20 |
| 9679810 | Integrated circuit having improved electromigration performance and method of forming same | Joyeeta Nag, Shishir Ray, Oleg Gluschenkov, Siddarth A. Krishnan, Michael P. Chudzik | 2017-06-13 |
| 9673089 | Interconnect structure with enhanced reliability | Griselda Bonilla, Kaushik Chanda, Robert D. Edwards, Ronald G. Filippi, Ping-Chuan Wang | 2017-06-06 |
| 9601426 | Interconnect structure having subtractive etch feature and damascene feature | Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Elbert E. Huang, Naftali E. Lustig | 2017-03-21 |
| 9601513 | Subsurface wires of integrated chip and methods of forming | Terence B. Hook, Andreas Scholze, Lars Liebmann, Roger QUON | 2017-03-21 |
| 9536842 | Structure with air gap crack stop | Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Xiao Hu Liu +1 more | 2017-01-03 |
| 9536830 | High performance refractory metal / copper interconnects to eliminate electromigration | Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig | 2017-01-03 |
| 9502350 | Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer | Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Elbert E. Huang, Naftali E. Lustig | 2016-11-22 |
| 9461017 | Electronic package that includes a plurality of integrated circuit devices bonded in a three-dimensional stack arrangement | Mukta G. Farooq, John A. Fitzsimmons, Anthony K. Stamper | 2016-10-04 |
| 9455186 | Selective local metal cap layer formation for improved electromigration behavior | Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp +4 more | 2016-09-27 |