Issued Patents All Time
Showing 51–75 of 113 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8921167 | Modified via bottom for BEOL via efuse | Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig | 2014-12-30 |
| 8916461 | Electronic fuse vias in interconnect structures | Junjing Bao, Griselda Bonilla, Samuel S. Choi, Daniel C. Edelstein, Ronald G. Filippi +1 more | 2014-12-23 |
| 8912658 | Interconnect structure with enhanced reliability | Ronald G. Filippi, Ping-Chuan Wang, Griselda Bonilla, Kaushik Chanda, Robert D. Edwards | 2014-12-16 |
| 8841212 | Method of making a copper interconnect having a barrier liner of multiple metal layers | Takeshi Nogami, Thomas M. Shaw, Jean Wynne, Chih-Chao Yang | 2014-09-23 |
| 8836124 | Fuse and integrated conductor | Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow +1 more | 2014-09-16 |
| 8765602 | Doping of copper wiring structures in back end of line processing | Thomas W. Dyer, Daniel C. Edelstein, Tze-man Ko, Wei-Tsu Tseng | 2014-07-01 |
| 8742766 | Stacked via structure for metal fuse applications | Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig +1 more | 2014-06-03 |
| 8741773 | Nickel-silicide formation with differential Pt composition | Asa Frye | 2014-06-03 |
| 8736020 | Electronic anti-fuse | Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig | 2014-05-27 |
| 8729702 | Copper seed layer for an interconnect structure having a doping concentration level gradient | Chengyu Niu, Keith Kwong Hon Wong, Yun-Yu Wang | 2014-05-20 |
| 8637925 | Nickel-silicide formation with differential Pt composition | Asa Frye | 2014-01-28 |
| 8633707 | Stacked via structure for metal fuse applications | Ronald G. Filippi, Griselda Bonilla, Kaushik Chanda, Stephan Grunow, Naftali E. Lustig +1 more | 2014-01-21 |
| 8552502 | Structure and method to make replacement metal gate and contact metal | Zhengwen Li, Michael P. Chudzik, Unoh Kwon, Filippos Papadatos, Keith Kwong Hon Wong | 2013-10-08 |
| 8343868 | Device and methodology for reducing effective dielectric constant in semiconductor devices | Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons +10 more | 2013-01-01 |
| 8298948 | Capping of copper interconnect lines in integrated circuit devices | Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, David L. Rath +3 more | 2012-10-30 |
| 8232148 | Structure and method to make replacement metal gate and contact metal | Zhengwen Li, Michael P. Chudzik, Unoh Kwon, Filippos Papadatos, Keith Kwong Hon Wong | 2012-07-31 |
| 8232646 | Interconnect structure for integrated circuits having enhanced electromigration resistance | Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Chao-Kun Hu +2 more | 2012-07-31 |
| 8129286 | Reducing effective dielectric constant in semiconductor devices | Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons +10 more | 2012-03-06 |
| 8056039 | Interconnect structure for integrated circuits having improved electromigration characteristics | Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Chao-Kun Hu, Sujatha Sankaran +1 more | 2011-11-08 |
| 7985928 | Gap free anchored conductor and dielectric structure and method for fabrication thereof | Tibor Bolom, Stephan Grunow, David L. Rath | 2011-07-26 |
| 7892940 | Device and methodology for reducing effective dielectric constant in semiconductor devices | Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons +10 more | 2011-02-22 |
| 7776737 | Reliability of wide interconnects | Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Sujatha Sankaran +1 more | 2010-08-17 |
| 7737528 | Structure and method of forming electrically blown metal fuses for integrated circuits | Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Jeffrey P. Gambino, Stephan Grunow +3 more | 2010-06-15 |
| 7704876 | Dual damascene interconnect structures having different materials for line and via conductors | Jeffrey P. Gambino, Edward C. Cooney, III, Anthony K. Stamper, William T. Motsiff, Michael Lane | 2010-04-27 |
| 7671362 | Test structure for determining optimal seed and liner layer thicknesses for dual damascene processing | Tibor Bolom, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Paul S. McLaughlin +3 more | 2010-03-02 |