Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
MH

Mark Hoinkis — 29 Patents

Infineon Technologies Ag: 20 patents #400 of 7,486Top 6%
IBM: 16 patents #6,980 of 70,183Top 10%
Applied Materials: 6 patents #1,938 of 7,310Top 30%
Siemens Aktiengesellschaft: 1 patents #10,653 of 22,248Top 50%
UMUnited Microelectronics: 1 patents #2,686 of 4,560Top 60%
Fishkill, NY: #24 of 387 inventorsTop 7%
New York: #4,236 of 115,490 inventorsTop 4%
Overall (All Time): #127,851 of 4,157,543Top 4%
29 Patents All Time
Mark Hoinkis has been granted 29 US patents while listed as an inventor at IBM. The first was granted in 1999 and the most recent in May 2018. Mark Hoinkis ranks #127,851 of 4,157,543 US inventors in our database (top 3.1%). Patent records list Mark Hoinkis in Fishkill, NY, US.

Patents per Year

Patents granted per year, 1999 to 2018Bar chart with a peak of 5 patents in 2006.peak 51999: 2 patents19992000: 2 patents2001: 4 patents20012002: 1 patents2003: 1 patents20032005: 3 patents2006: 5 patents20062007: 2 patents2008: 1 patents20082009: 1 patents2010: 1 patents20102014: 1 patents2015: 2 patents20152016: 2 patents2018: 1 patents2018

Issued Patents All Time

Showing 1–25 of 29 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9960052 Methods for etching a metal layer to form an interconnection structure for semiconductor applications Sumit Agarwal, Ann Chien, Chiu-pien KUO, Bradley J. Howard 2018-05-01 $18,276,000
9493879 Selective sputtering for pattern transfer Hiroyuki Miyazoe, Eric A. Joseph 2016-11-15 $32,851,000
9484220 Sputter etch processing for heavy metal patterning in integrated circuits Eric A. Joseph, Hiroyuki Miyazoe, Chun Yan 2016-11-01 $3,150,000
9171796 Sidewall image transfer for heavy metal patterning in integrated circuits Markus Brink, Michael A. Guillorn, Eric A. Joseph, Hiroyuki Miyazoe, Bang N. To 2015-10-27 $4,228,000
9114438 Copper residue chamber clean Chun Yan, Hiroyuki Miyazoe, Eric A. Joseph 2015-08-25 $10,519,000
8871107 Subtractive plasma etching of a blanket layer of metal or metal alloy Nicholas C. M. Fuller, Eric A. Joseph, Hiroyuki Miyazoe, Chun Yan 2014-10-28 $3,762,000
7786007 Method and apparatus of stress relief in semiconductor structures Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu 2010-08-31
7494915 Back end interconnect with a shaped interface Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Steffen K. Kaldor, Erdem Kaltalioglu +8 more 2009-02-24
7368804 Method and apparatus of stress relief in semiconductor structures Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu 2008-05-06 $508,000
7241681 Bilayered metal hardmasks for use in dual damascene etch schemes Kaushik A. Kumar, Lawrence A. Clevenger, Timothy J. Dalton, Douglas C. La Tulipe, Jr., Andy Cowley +5 more 2007-07-10
7241696 Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer Larry Clevenger, Timothy J. Dalton, Steffen K. Kaldor, Kaushik A. Kumar, Douglas C. La Tulipe, Jr. +5 more 2007-07-10
7122462 Back end interconnect with a shaped interface Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Steffen K. Kaldor, Erdem Kaltalioglu +8 more 2006-10-17
7091612 Dual damascene structure and method Kaushik A. Kumar, Timothy J. Dalton, Larry Clevenger, Andy Cowley, Douglas C. La Tulipe, Jr. +5 more 2006-08-15
7060619 Reduction of the shear stress in copper via's in organic interlayer dielectric material Andy Cowley, Erdem Kaltalioglu, Michael Stetter 2006-06-13 $121,000
7052621 Bilayered metal hardmasks for use in Dual Damascene etch schemes Kaushik A. Kumar, Lawrence A. Clevenger, Timothy J. Dalton, Douglas C. La Tulipe, Jr., Andy Cowley +5 more 2006-05-30
7001835 Crystallographic modification of hard mask properties Lawrence A. Clevenger, Andrew P. Cowley, Timothy J. Dalton, Steffen K. Kaldor, Kaushik A. Kumar +3 more 2006-02-21
6960835 Stress-relief layer for semiconductor applications Hans-Joachim Barth, Erdem Kaltalioglu, Gerald Friese, Pak K. Leung 2005-11-01
6870263 Device interconnection Lawrence A. Clevenger, Ronald G. Filippi, Jeffery L. Hurd, Roy Iggulden, Herbert Palm +5 more 2005-03-22 $80,000
6864171 Via density rules Matthias Hierlemann, Mohammed Fazil Fayaz, Andy Cowley, Erdum Kaltalioglu 2005-03-08 $71,000
6539625 Chromium adhesion layer for copper vias in low-k technology Brett H. Engel, John A. Miller, Soon-Cheon Seo, Yun-Yu Wang, Kwong Hon Wong 2003-04-01
6383929 Copper vias in low-k technology Steven H. Boettcher, Herbert L. Ho, Hyun Koo Lee, Yun-Yu Wang, Kwong Hon Wong 2002-05-07
6242789 Vertical fuse and method of fabrication Stefan Weber, Axel Brintzinger, Roy Iggulden, Chandrasekhar Narayan, Robert Willem Van Den Berg 2001-06-05
6221757 Method of making a microelectronic structure Sven Schmidbauer, Alexander Ruf, Florian Schnabel, Stefan Weber 2001-04-24 $5,077,000
6218279 Vertical fuse and method of fabrication Stefan Weber, Axel Brintzinger, Roy Iggulden, Chandrasekhar Narayan, Robert Willem Van Den Berg 2001-04-17
6218298 Tungsten-filled deep trenches 2001-04-17 $1,450,000