Issued Patents All Time
Showing 25 most recent of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10600687 | Process integration techniques using a carbon layer to form self-aligned structures | Aelan Mosden | 2020-03-24 |
| 10079151 | Method for bottom-up deposition of a film in a recessed feature | Kandabara Tapily, David L. O'Meara | 2018-09-18 |
| 9653319 | Method for using post-processing methods for accelerating EUV lithography | Anton J. deVilliers | 2017-05-16 |
| 9153457 | Etch process for reducing directed self assembly pattern defectivity using direct current positioning | Vidhya Chakrapani, Akiteru Ko | 2015-10-06 |
| 8945408 | Etch process for reducing directed self assembly pattern defectivity | Vidhya Chakrapani, Akiteru Ko | 2015-02-03 |
| 8808562 | Dry metal etching method | Yusuke Ohsawa, Hiroto Ohtake, Eiji Suzuki, Andrew Metz | 2014-08-19 |
| 8809194 | Formation of SiOCl-containing layer on spacer sidewalls to prevent CD loss during spacer etch | Alok Ranjan | 2014-08-19 |
| 8664012 | Combined silicon oxide etch and contamination removal process | Richard H. Gaylord, Blaze Messer | 2014-03-04 |
| 8592327 | Formation of SiOCl-containing layer on exposed low-k surfaces to reduce low-k damage | Alok Ranjan | 2013-11-26 |
| 8551877 | Sidewall and chamfer protection during hard mask removal for interconnect patterning | Alok Ranjan | 2013-10-08 |
| 8492295 | On-chip cooling for integrated circuits | Andres Fernando Munoz, Michael Sievers, Richard S. Wise | 2013-07-23 |
| 8367544 | Self-aligned patterned etch stop layers for semiconductor devices | Kangguo Cheng, Lawrence A. Clevenger, Johnathan E. Faltermeier, Stephan Grunow, Kevin S. Petrarca | 2013-02-05 |
| 8298966 | On-chip cooling systems for integrated circuits | Andres Fernando Munoz, Michael Sievers, Richard S. Wise | 2012-10-30 |
| 8058176 | Methods of patterning insulating layers using etching techniques that compensate for etch rate variations | Wan Jae Park, Joseph Edward Linville, Anthony D. Lisi, Ravi Prakash Srivastava, Hermann Wendt | 2011-11-15 |
| 8030157 | Liner protection in deep trench etching | Habib Hichri, Ahmad D. Katnani, Narender Rana, Richard S. Wise, Hakeem B. S. Akinmade-Yusuff | 2011-10-04 |
| 8008209 | Thermal gradient control of high aspect ratio etching and deposition processes | Michael Sievers, Andres Fernando Munoz, Richard S. Wise | 2011-08-30 |
| 7888252 | Self-aligned contact | Johnathan E. Faltermeier, Stephan Grunow, Kangguo Cheng, Kevin S. Petrarca, Lawrence A. Clevenger +2 more | 2011-02-15 |
| 7879717 | Polycarbosilane buried etch stops in interconnect structures | Elbert E. Huang, Kelly Malone, Dirk Pfeiffer, Muthumanickam Sankarapandian, Christy S. Tyberg | 2011-02-01 |
| 7851919 | Metal interconnect and IC chip including metal interconnect | Karl W. Barth, Ramona Kei, Kevin S. Petrarca, Shahab Siddiqui | 2010-12-14 |
| 7833893 | Method for forming conductive structures | Stephan Grunow, Kevin S. Petrarca, Richard P. Volant | 2010-11-16 |
| 7825019 | Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits | Lawrence A. Clevenger, Stephan Grunow, Kevin S. Petrarca, Vidhya Ramachandran | 2010-11-02 |
| 7737561 | Dual damascene integration of ultra low dielectric constant porous materials | Kelly Malone, Christy S. Tyberg | 2010-06-15 |
| 7732288 | Method for fabricating a semiconductor structure | Huilong Zhu, Lawrence A. Clevenger, Omer H. Dokumaci, Oleg Gluschenkov, Carl Radens +1 more | 2010-06-08 |
| 7718525 | Metal interconnect forming methods and IC chip including metal interconnect | Karl W. Barth, Ramona Kei, Kevin S. Petrarca, Shahab Siddiqui | 2010-05-18 |
| 7696025 | Sidewall semiconductor transistors | Huilong Zhu, Lawrence A. Clevenger, Omer H. Dokumaci, Carl Radens, Dureseti Chidambarrao | 2010-04-13 |