Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12185477 | Method for making printed wiring board, printed wiring board, and adhesive film for making printed wiring board | — | 2024-12-31 |
| 10898932 | Method and apparatus for cleaning a substrate and computer program product | Uwe Dietze, Seongkuk Lee, Davide Dattilo, Martin Samayoa | 2021-01-26 |
| 9779932 | Sacrificial layer for post-laser debris removal systems | — | 2017-10-03 |
| 9064848 | ARC residue-free etching | Xiang Hu, Richard Wise, Catherine B. Labelle | 2015-06-23 |
| 8901005 | Method for simultaneously forming features of different depths in a semiconductor substrate | Xi Li, Richard S. Wise | 2014-12-02 |
| 8901006 | ARC residue-free etching | Xiang Hu, Richard Wise, Catherine B. Labelle | 2014-12-02 |
| 8822342 | Method to reduce depth delta between dense and wide features in dual damascene structures | Ravi Prakash Srivastava, Oluwafemi. O. Ogunsola, Craig Child, Muhammed Shafi Pallachalil, Matthew S. Angyal +1 more | 2014-09-02 |
| 8735284 | Conductive metal and diffusion barrier seed compositions, and methods of use in semiconductor and interlevel dielectric substrates | Kelly Malone | 2014-05-27 |
| 8647535 | Conductive metal and diffusion barrier seed compositions, and methods of use in semiconductor and interlevel dielectric substrates | Kelly Malone | 2014-02-11 |
| 8642475 | Integrated circuit system with reduced polysilicon residue and method of manufacture thereof | Xiang Hu, Helen Wang, Arifuzzaman (Arif) Sheikh, Richard Wise | 2014-02-04 |
| 8492280 | Method for simultaneously forming features of different depths in a semiconductor substrate | Xi Li, Richard S. Wise | 2013-07-23 |
| 8168451 | Optical inspection methods | Colin J. Brodsky, Mary Jane Brodsky, Sean D. Burns | 2012-05-01 |
| 8030157 | Liner protection in deep trench etching | Ahmad D. Katnani, Kaushik A. Kumar, Narender Rana, Richard S. Wise, Hakeem B. S. Akinmade-Yusuff | 2011-10-04 |
| 7645621 | Optical inspection methods | Colin J. Brodsky, Mary Jane Brodsky, Sean D. Burns | 2010-01-12 |
| 7544609 | Method for integrating liner formation in back end of line processing | Matthew S. Angyal, Christopher J. Penny, David Watts | 2009-06-09 |
| 7475368 | Deflection analysis system and method for circuit design | Matthew S. Angyal, Giovanni Fiorenza, Andrew Lu, Dale Curtis McHerron, Conal E. Murray | 2009-01-06 |
| 7456098 | Building metal pillars in a chip for structure support | Xiao Hu Liu, Vincent J. McGahay, Conal E. Murray, Jawahar P. Nayak, Thomas M. Shaw | 2008-11-25 |
| 7279426 | Like integrated circuit devices with different depth | Kimberly Larsen, Helen L. Maynard, Kevin S. Petrarca | 2007-10-09 |
| 7253100 | Reducing damage to ulk dielectric during cross-linked polymer removal | Ronald A. DellaGuardia, Daniel C. Edelstein, Vincent J. McGahay | 2007-08-07 |
| 7214608 | Interlevel dielectric layer and metal layer sealing | Matthew S. Angyal, Peter Biolsi, Lawrence A. Clevenger, Bernd Kastenmeier, Michael Lane +3 more | 2007-05-08 |
| 7135398 | Reliable low-k interconnect structure with hybrid dielectric | John A. Fitzsimmons, Stephen E. Greco, Jia Lee, Stephen M. Gates, Terry A. Spooner +3 more | 2006-11-14 |
| 7067902 | Building metal pillars in a chip for structure support | Xiao Hu Liu, Vincent J. McGahay, Conal E. Murray, Jawahar P. Nayak, Thomas M. Shaw | 2006-06-27 |
| 7009280 | Low-k interlevel dielectric layer (ILD) | Matthew S. Angyal, Edward Barth, Sanjit Das, Charles R. Davis, William Francis Landers +1 more | 2006-03-07 |
| 6917108 | Reliable low-k interconnect structure with hybrid dielectric | John A. Fitzsimmons, Stephen E. Greco, Jia Lee, Stephen M. Gates, Terry A. Spooner +3 more | 2005-07-12 |
| 6831363 | Structure and method for reducing thermo-mechanical stress in stacked vias | Timothy J. Dalton, Sanjit Das, Brett H. Engel, Brian Herbst, Bernd Kastenmeier +8 more | 2004-12-14 |