Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12300500 | Etching of polycrystalline semiconductors | Yun Han, Alok Ranjan, Tomoyuki Oishi, Shuhei Ogawa, Ken Kobayashi | 2025-05-13 |
| 12266533 | Sacrificial capping layer for contact etch | Yun Han, Andrew Metz | 2025-04-01 |
| 8614150 | Methods of manufacturing semiconductor structures using RIE process | Samuel S. Choi, Kevin J. Mackey | 2013-12-24 |
| 8532796 | Contact processing using multi-input/multi-output (MIMO) models | Daniel Prager, Merritt Funk, Ryukichi Shimizu | 2013-09-10 |
| 7442650 | Methods of manufacturing semiconductor structures using RIE process | Samuel S. Choi, Kevin J. Mackey | 2008-10-28 |
| 7214608 | Interlevel dielectric layer and metal layer sealing | Matthew S. Angyal, Lawrence A. Clevenger, Habib Hichri, Bernd Kastenmeier, Michael Lane +3 more | 2007-05-08 |
| 7045464 | Via reactive ion etching process | Samuel S. Choi | 2006-05-16 |
| 7030031 | Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material | William C. Wille, Daniel C. Edelstein, William J. Cote, John Fritche, Allan Upham | 2006-04-18 |
| 6677678 | Damascene structure using a sacrificial conductive layer | Gregory S. Jankowski, Laurie M. Krywanczyk, Anthony K. Stamper | 2004-01-13 |
| 6444557 | Method of forming a damascene structure using a sacrificial conductive layer | Gregory S. Jankowski, Laurie M. Krywanczyk, Anthony K. Stamper | 2002-09-03 |