| 7838390 |
Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein |
Jun Jung Kim, Joo-chan Kim, Jae-eon Park, Richard A. Conti, Zhao Lun +2 more |
2010-11-23 |
| 7635899 |
Structure and method to form improved isolation in a semiconductor device |
Haining Yang, Thomas W. Dyer |
2009-12-22 |
| 7550364 |
Stress engineering using dual pad nitride with selective SOI device architecture |
Dureseti Chidambarrao, William K. Henson, Kern Rim |
2009-06-23 |
| 7202513 |
Stress engineering using dual pad nitride with selective SOI device architecture |
Dureseti Chidambarrao, William K. Henson, Kern Rim |
2007-04-10 |
| 7183130 |
Magnetic random access memory and method of fabricating thereof |
Joachim Nuetzel, Xian Jay Ning |
2007-02-27 |
| 7030031 |
Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material |
Daniel C. Edelstein, William J. Cote, Peter Biolsi, John Fritche, Allan Upham |
2006-04-18 |
| 6762667 |
Micro electromechanical switch having self-aligned spacers |
Richard P. Volant, David Angell, Donald F. Canaperi, Joseph T. Kocis, Kevin S. Petrarca +1 more |
2004-07-13 |
| 6621392 |
Micro electromechanical switch having self-aligned spacers |
Richard P. Volant, David Angell, Donald F. Canaperi, Joseph T. Kocis, Kevin S. Petrarca +1 more |
2003-09-16 |
| 6593617 |
Field effect transistors with vertical gate side walls and method for making such transistors |
Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, Yuan Taur |
2003-07-15 |
| 6461529 |
Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme |
Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, Waldemar Walter Kocon, Richard S. Wise |
2002-10-08 |
| 6361402 |
Method for planarizing photoresist |
Donald F. Canaperi, Rangarajan Jagannathan, Mahadevaiyer Krishnan, Max G. Levy, Uma Satyendra +2 more |
2002-03-26 |
| 6207353 |
Resist formulation which minimizes blistering during etching |
Michael D. Armacost, Willard E. Conley, Tina J. Cotler-Wagner, Ronald A. DellaGuardia, David M. Dobuzinsky +1 more |
2001-03-27 |
| 6143635 |
Field effect transistors with improved implants and method for making such transistors |
Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, Yuan Taur |
2000-11-07 |
| 6093281 |
Baffle plate design for decreasing conductance lost during precipitation of polymer precursors in plasma etching chambers |
Richard Wise, David M. Dobuzinsky |
2000-07-25 |
| 6040214 |
Method for making field effect transistors having sub-lithographic gates with vertical side walls |
Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, Yuan Taur |
2000-03-21 |
| 5976982 |
Methods for protecting device components from chemical mechanical polish induced defects |
Max G. Levy, Wolfgang Bergner, Bernhard Fiegl, George R. Goth, Paul C. Parries +3 more |
1999-11-02 |
| 5811357 |
Process of etching an oxide layer |
Michael D. Armacost, Tina Wagner, Michael L. Passow, Dominic J. Schepis, Matthew Sendelbach |
1998-09-22 |
