WK

Waldemar Walter Kocon

IBM: 14 patents #8,004 of 70,183Top 15%
KT Kabushiki Kaisha Toshiba: 1 patents #13,537 of 21,451Top 65%
SA Siemens Aktiengesellschaft: 1 patents #10,653 of 22,248Top 50%
SC Siemens Components: 1 patents #6 of 30Top 20%
Overall (All Time): #354,738 of 4,157,543Top 9%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7855137 Method of making a sidewall-protected metallic pillar on a semiconductor substrate Mukta G. Farooq, Kevin S. Petrarca, Richard P. Volant 2010-12-21
6461529 Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme Diane C. Boyd, Stuart M. Burns, Hussein I. Hanafi, William C. Wille, Richard S. Wise 2002-10-08
6375859 Process for resist clean up of metal structures on polyimide Richard P. Volant, Joseph T. Kocis, Seshadri Subbanna 2002-04-23
6268226 Reactive ion etch loading measurement technique David Angell, Stuart M. Burns, Michael L. Passow 2001-07-31
6077745 Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array Stuart M. Burns, Hussein I. Hanafi, Jeffrey J. Welser, Howard L. Kalter 2000-06-20
6034389 Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array Stuart M. Burns, Hussein I. Hanafi, Howard L. Kalter, Jeffrey J. Welser 2000-03-07
6033957 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation Stuart M. Burns, Hussein I. Hanafi, Jeffrey J. Welser 2000-03-07
6013548 Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array Stuart M. Burns, Hussein I. Hanafi, Howard L. Kalter, Jeffrey J. Welser 2000-01-11
5929477 Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array Stuart McAllister Burns, Jr., Hussein I. Hanafi, Jeffrey J. Welser, Howard L. Kalter 1999-07-27
5895273 Silicon sidewall etching Stuart M. Burns, Hussein I. Hanafi, Jeffrey J. Welser 1999-04-20
5874760 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation Stuart M. Burns, Hussein I. Hanafi, Jeffrey J. Welser 1999-02-23
5874363 Polycide etching with HCL and chlorine Peter D. Hoh, Tokuhisa Ohiwa, Virinder Grewal, Bruno Spuler, Guadalupe Wiltshire 1999-02-23
5759920 Process for making doped polysilicon layers on sidewalls Stuart M. Burns, Hussein I. Hanafi 1998-06-02
5670018 Isotropic silicon etch process that is highly selective to tungsten Elke Eckstein, Birgit Hoffman, deceased, Edward W. Kiewra, Marc Jay Weiss 1997-09-23