Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6593617 | Field effect transistors with vertical gate side walls and method for making such transistors | Diane C. Boyd, Hussein I. Hanafi, Yuan Taur, William C. Wille | 2003-07-15 |
| 6461529 | Anisotropic nitride etch process with high selectivity to oxide and photoresist layers in a damascene etch scheme | Diane C. Boyd, Hussein I. Hanafi, Waldemar Walter Kocon, William C. Wille, Richard S. Wise | 2002-10-08 |
| 6268226 | Reactive ion etch loading measurement technique | David Angell, Waldemar Walter Kocon, Michael L. Passow | 2001-07-31 |
| 6258679 | Sacrificial silicon sidewall for damascene gate formation | Hussein I. Hanafi | 2001-07-10 |
| 6143635 | Field effect transistors with improved implants and method for making such transistors | Diane C. Boyd, Hussein I. Hanafi, Yuan Taur, William C. Wille | 2000-11-07 |
| 6077745 | Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array | Hussein I. Hanafi, Jeffrey J. Welser, Waldemar Walter Kocon, Howard L. Kalter | 2000-06-20 |
| 6040214 | Method for making field effect transistors having sub-lithographic gates with vertical side walls | Diane C. Boyd, Hussein I. Hanafi, Yuan Taur, William C. Wille | 2000-03-21 |
| 6040210 | 2F-square memory cell for gigabit memory applications | Hussein I. Hanafi | 2000-03-21 |
| 6033957 | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation | Hussein I. Hanafi, Jeffrey J. Welser, Waldemar Walter Kocon | 2000-03-07 |
| 6034389 | Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array | Hussein I. Hanafi, Howard L. Kalter, Jeffrey J. Welser, Waldemar Walter Kocon | 2000-03-07 |
| 6013548 | Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array | Hussein I. Hanafi, Howard L. Kalter, Jeffrey J. Welser, Waldemar Walter Kocon | 2000-01-11 |
| 5990509 | 2F-square memory cell for gigabit memory applications | Hussein J. Hanafi, Jeffrey J. Welser | 1999-11-23 |
| 5976986 | Low pressure and low power C1.sub.2 /HC1 process for sub-micron metal etching | Munir D. Naeem, Rosemary Christie, Virinder Grewal, Walter W. Kocon, Masaki Narita +2 more | 1999-11-02 |
| 5895273 | Silicon sidewall etching | Hussein I. Hanafi, Waldemar Walter Kocon, Jeffrey J. Welser | 1999-04-20 |
| 5874760 | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation | Hussein I. Hanafi, Jeffrey J. Welser, Waldemar Walter Kocon | 1999-02-23 |
| 5846884 | Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing | Munir D. Naeem, Nancy Anne Greco, STEVE GRECO, Virinder Grewal, Ernest N. Levine +2 more | 1998-12-08 |
| 5759920 | Process for making doped polysilicon layers on sidewalls | Hussein I. Hanafi, Waldemar Walter Kocon | 1998-06-02 |