Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7658969 | Chemical vapor deposition chamber with dual frequency bias and method for manufacturing a photomask using the same | Ajay Kumar, Wai-Fan Yau | 2010-02-09 |
| 6897155 | Method for etching high-aspect-ratio features | Ajay Kumar, Anisul Khan, Dragan Podlesnik, Sharma Pamarthy, Axel Henke +1 more | 2005-05-24 |
| 6300235 | Method of forming multi-level coplanar metal/insulator films using dual damascene with sacrificial flowable oxide | Klaus Feldner, Bernd Vollmer, Rainer Florian Schnabel | 2001-10-09 |
| 6071820 | Method for patterning integrated circuit conductors | Bruno Spuler | 2000-06-06 |
| 6008121 | Etching high aspect contact holes in solid state devices | Chi-Hua Yang, Volker B. Laux | 1999-12-28 |
| 5976986 | Low pressure and low power C1.sub.2 /HC1 process for sub-micron metal etching | Munir D. Naeem, Stuart M. Burns, Rosemary Christie, Walter W. Kocon, Masaki Narita +2 more | 1999-11-02 |
| 5926689 | Process for reducing circuit damage during PECVD in single wafer PECVD system | Donna R. Cote, John C. Forster, Anthony Konecni, Dragan Podlesnik | 1999-07-20 |
| 5874363 | Polycide etching with HCL and chlorine | Peter D. Hoh, Tokuhisa Ohiwa, Bruno Spuler, Waldemar Walter Kocon, Guadalupe Wiltshire | 1999-02-23 |
| 5846884 | Methods for metal etching with reduced sidewall build up during integrated circuit manufacturing | Munir D. Naeem, Stuart M. Burns, Nancy Anne Greco, STEVE GRECO, Ernest N. Levine +2 more | 1998-12-08 |
| 5723381 | Formation of self-aligned overlapping bitline contacts with sacrificial polysilicon fill-in stud | Bernhard Poschenrieder | 1998-03-03 |
| 5597438 | Etch chamber having three independently controlled electrodes | Volker B. Laux | 1997-01-28 |
| 5591301 | Plasma etching method | — | 1997-01-07 |
| 5529197 | Polysilicon/polycide etch process for sub-micron gate stacks | — | 1996-06-25 |
| 5262002 | Method for manufacturing a trench structure in a substrate | Siegfried Schwarzl | 1993-11-16 |
| 5212114 | Process for global planarizing of surfaces for integrated semiconductor circuits | Klaus-Dieter Menz, Ronald Huber | 1993-05-18 |
| 4764245 | Method for generating contact holes with beveled sidewalls in intermediate oxide layers | — | 1988-08-16 |
| 4482209 | Mirror structure | Werner Reindl | 1984-11-13 |
| 4372809 | Method for manufacturing solderable, temperable, thin film tracks which do not contain precious metal | Werner Reindl | 1983-02-08 |