GG

George R. Goth

IBM: 19 patents #5,782 of 70,183Top 9%
SA Siemens Aktiengesellschaft: 2 patents #6,658 of 22,248Top 30%
Overall (All Time): #225,994 of 4,157,543Top 6%
20
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6967375 Reduction of chemical mechanical planarization (CMP) scratches with sacrificial dielectric polish stop Rainer E. Gehres 2005-11-22
6518145 Methods to control the threshold voltage of a deep trench corner device Johann Alsmeier, Max G. Levy, Victor R. Nastasi, James A. O'Neill, Paul C. Parries 2003-02-11
6021360 Process controller for balancing usage of tool sets Brian C. Barker, John T. Federico, Perry G. Hartswick 2000-02-01
5976982 Methods for protecting device components from chemical mechanical polish induced defects Max G. Levy, Wolfgang Bergner, Bernhard Fiegl, Paul C. Parries, Matthew Sendelbach +3 more 1999-11-02
4824797 Self-aligned channel stop — 1989-04-25
4758528 Self-aligned metal process for integrated circuit metallization Ingrid E. Magdo, Shashi D. Malaviya 1988-07-19
4743565 Lateral device structures using self-aligned fabrication techniques Shashi D. Malaviya 1988-05-10
4719185 Method of making shallow junction complementary vertical bipolar transistor pair — 1988-01-12
4717678 Method of forming self-aligned P contact — 1988-01-05
4704368 Method of making trench-incorporated monolithic semiconductor capacitor and high density dynamic memory cells including the capacitor Shashi D. Malaviya 1987-11-03
4691219 Self-aligned polysilicon base contact structure — 1987-09-01
4688073 Lateral device structures using self-aligned fabrication techniques Shashi D. Malaviya 1987-08-18
4665007 Planarization process for organic filling of deep trenches Nancy R. Cservak, Susan K. Fribley, Mark A. Takacs 1987-05-12
4608589 Self-aligned metal structure for integrated circuits Ingrid E. Magdo, Shashi D. Malaviya 1986-08-26
4589193 Metal silicide channel stoppers for integrated circuits and method for making the same Thomas Hansen, Robert T. Villetto, Jr. 1986-05-20
4549927 Method of selectively exposing the sidewalls of a trench and its use to the forming of a metal silicide substrate contact for dielectric filled deep trench isolated devices Thomas Hansen, James S. Makris 1985-10-29
4541168 Method for making metal contact studs between first level metal and regions of a semiconductor device compatible with polyimide-filled deep trench isolation schemes John R. Galie, Thomas Hansen, Robert T. Villetto, Jr. 1985-09-17
4534826 Trench etch process for dielectric isolation Thomas Hansen, Robert T. Villetto, Jr. 1985-08-13
4508579 Lateral device structures using self-aligned fabrication techniques Shashi D. Malaviya 1985-04-02
4400865 Self-aligned metal process for integrated circuit metallization Ingrid E. Magdo, Shashi D. Malaviya 1983-08-30