Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Daniel Prager — 21 Patents

TLTokyo Electron Limited: 19 patents #307 of 5,567Top 6%
IBM: 4 patents #21,783 of 70,183Top 35%
TTTimbre Technologies: 2 patents #13 of 39Top 35%
Hopewell Junction, NY: #86 of 648 inventorsTop 15%
New York: #6,583 of 115,490 inventorsTop 6%
Overall (All Time): #201,324 of 4,157,543Top 5%
21 Patents All Time
Daniel Prager has been granted 21 US patents while listed as an inventor at Tokyo Electron Limited. The first was granted in 2006 and the most recent in September 2013. Daniel Prager ranks #201,324 of 4,157,543 US inventors in our database (top 4.8%). Patent records list Daniel Prager in Hopewell Junction, NY, US.

Issued Patents All Time

Showing 1–21 of 21 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8532796 Contact processing using multi-input/multi-output (MIMO) models Merritt Funk, Peter Biolsi, Ryukichi Shimizu 2013-09-10
8501628 Differential metal gate etching process Vinh Luong, Hiroyuki Takahashi, Akiteru Ko, Asao Yamashita, Vaidya Bharadwaj +1 more 2013-08-06
8183062 Creating metal gate structures using Lithography-Etch-Lithography-Etch (LELE) processing sequences Merritt Funk, Radha Sundararajan, Asao Yamashita 2012-05-22
8019458 Creating multi-layer/multi-input/multi-output (MLMIMO) models for metal-gate structures Merritt Funk, Radha Sundararajan, Asao Yamashita, Hyung Joo Lee 2011-09-13
7967995 Multi-layer/multi-input/multi-output (MLMIMO) models and method for using Merritt Funk, Radha Sundararajan, Hyung Joo Lee, Asao Yamashita 2011-06-28
7939450 Method and apparatus for spacer-optimization (S-O) Asao Yamashita, Merritt Funk, Lee Chen, Radha Sundararajan 2011-05-10
7899637 Method and apparatus for creating a gate optimization evaluation library Asao Yamashita, Merritt Funk, Lee Chen, Radha Sundararajan 2011-03-01
7894927 Using Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models for metal-gate structures Merritt Funk, Radha Sundararajan, Asao Yamashita, Hyung Joo Lee 2011-02-22
7765077 Method and apparatus for creating a Spacer-Optimization (S-O) library Asao Yamashita, Merritt Funk, Lee Chen, Radha Sundaranajan 2010-07-27
7713758 Method and apparatus for optimizing a gate channel Asao Yamashita, Merritt Funk, Lee Chen, Radha Sundararajan 2010-05-11
7567700 Dynamic metrology sampling with wafer uniformity control Merritt Funk, Radha Sundararajan, Wesley C. Natzle 2009-07-28 $11,761,000
7542859 Creating a virtual profile library Merritt Funk 2009-06-02
7502660 Feature dimension deviation correction system, method and program product David V. Horak, Wesley C. Natzle, Merritt Funk, Kevin Lally 2009-03-10 $6,331,000
7502709 Dynamic metrology sampling for a dual damascene process Merritt Funk, Radha Sundararajan, Wesley C. Natzle 2009-03-10 $6,331,000
7487053 Refining a virtual profile library Merritt Funk 2009-02-03
7395132 Optical metrology model optimization for process control Jason Ferns, Lawrence Lane, Dan Engelhard 2008-07-01
7328418 Iso/nested control for soft mask processing Asao Yamashita, Merritt Funk 2008-02-05
7305322 Using a virtual profile library Merritt Funk 2007-12-04
7289864 Feature dimension deviation correction system, method and program product David V. Horak, Wesley C. Natzle, Merritt Funk, Kevin Lally 2007-10-30 $4,304,000
7209798 Iso/nested cascading trim control with model feedback updates Asao Yamashita, Merritt Funk 2007-04-24
7126700 Parametric optimization of optical metrology model Junwei Bao, Vi Vuong, Manuel Madriaga 2006-10-24