Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11417525 | Multiple patterning with mandrel cuts defined by block masks | Martin O'Toole, Keith Donegan, Brendan O'Brien, Hsueh-Chung Chen, Terry A. Spooner +4 more | 2022-08-16 |
| 11367750 | Vertical memory devices | Sunil Kumar Singh, Xuan Anh Tran, Eswar Ramanathan, Suryanarayana Kalaga, Robert FOX | 2022-06-21 |
| 10643891 | Via structures and via patterning using oblique angle deposition processes | Qanit Takmeel, Somnath Ghosh, Anbu Selvam K M Mahalingam, Sunil Kumar Singh | 2020-05-05 |
| 10566231 | Interconnect formation with chamferless via, and related interconnect | Martin O'Toole, Christopher J. Penny, Jae-ouk Choo, Adam L. da Silva, Terry A. Spooner +3 more | 2020-02-18 |
| 10340177 | Devices and methods of reducing damage during BEOL M1 integration | Ashwini Chandrashekar, Anbu Selvam KM Mahalingam | 2019-07-02 |
| 10181420 | Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias | Jason E. Stephens, David Permana, Guillaume Bouche, Andy Wei, Mark A. Zaleski +6 more | 2019-01-15 |
| 9818623 | Method of forming a pattern for interconnection lines and associated continuity blocks in an integrated circuit | Jason E. Stephens, Guillaume Bouche, Byoung Youp Kim | 2017-11-14 |
| 9812396 | Interconnect structure for semiconductor devices with multiple power rails and redundancy | Jason E. Stephens, Guillaume Bouche, Shreesh Narasimha, Patrick R. Justison, Byoung Youp Kim | 2017-11-07 |
| 9786545 | Method of forming ANA regions in an integrated circuit | Guillaume Bouche, Jason E. Stephens, Byoung Youp Kim, Shreesh Narasimha | 2017-10-10 |
| 9691971 | Integrated circuits including magnetic tunnel junctions for magnetoresistive random-access memory and methods for fabricating the same | Seowoo Nam, Ming He, Hyun-Jin Cho | 2017-06-27 |
| 9431294 | Methods of producing integrated circuits with an air gap | Ming He, Errol Todd Ryan, Roderick A. Augur, Larry Zhao | 2016-08-30 |
| 9165770 | Methods for fabricating integrated circuits using improved masks | Ming He, Seowoo Nam | 2015-10-20 |
| 8822342 | Method to reduce depth delta between dense and wide features in dual damascene structures | Ravi Prakash Srivastava, Oluwafemi. O. Ogunsola, Muhammed Shafi Pallachalil, Habib Hichri, Matthew S. Angyal +1 more | 2014-09-02 |
| 8513109 | Method of manufacturing an interconnect structure for a semiconductor device | — | 2013-08-20 |
| 7932613 | Interconnect structure for a semiconductor device | — | 2011-04-26 |