Issued Patents All Time
Showing 25 most recent of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10169525 | Multiple-depth trench interconnect technology at advanced semiconductor nodes | Vincent J. McGahay, Rasit Onur Topaloglu | 2019-01-01 |
| 10152567 | Early overlay prediction and overlay-aware mask design | Rasit Onur Topaloglu | 2018-12-11 |
| 9940429 | Early overlay prediction and overlay-aware mask design | Rasit Onur Topaloglu | 2018-04-10 |
| 9710592 | Multiple-depth trench interconnect technology at advanced semiconductor nodes | Vincent J. McGahay, Rasit Onur Topaloglu | 2017-07-18 |
| 9601367 | Interconnect level structures for confining stitch-induced via structures | Rasit Onur Topaloglu | 2017-03-21 |
| 9589912 | Integrated circuit structure with crack stop and method of forming same | Jim Shih-Chun Liang, Atsushi Ogino, Roger QUON | 2017-03-07 |
| 9589911 | Integrated circuit structure with metal crack stop and methods of forming same | Jim Shih-Chun Liang, Atsushi Ogino, Roger QUON | 2017-03-07 |
| 9454631 | Stitch-derived via structures and methods of generating the same | Vincent J. McGahay, Rasit Onur Topaloglu | 2016-09-27 |
| 9455186 | Selective local metal cap layer formation for improved electromigration behavior | Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp +4 more | 2016-09-27 |
| 9424388 | Dividing lithography exposure fields to improve semiconductor fabrication | Rasit Onur Topaloglu | 2016-08-23 |
| 9406560 | Selective local metal cap layer formation for improved electromigration behavior | Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp +4 more | 2016-08-02 |
| 9385038 | Selective local metal cap layer formation for improved electromigration behavior | Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp +4 more | 2016-07-05 |
| 9373538 | Interconnect level structures for confining stitch-induced via structures | Rasit Onur Topaloglu | 2016-06-21 |
| 9157980 | Measuring metal line spacing in semiconductor devices | Thomas W. Dyer | 2015-10-13 |
| 9075944 | System and method of predicting problematic areas for lithography in a circuit design | Timothy A. Brunner, Bernhard R. Liegl, Hua Xiang | 2015-07-07 |
| 9076847 | Selective local metal cap layer formation for improved electromigration behavior | Matthew S. Angyal, Junjing Bao, Griselda Bonilla, Samuel S. Choi, James A. Culp +4 more | 2015-07-07 |
| 9058457 | Reticle data decomposition for focal plane determination in lithographic processes | Ian P. Stobert, Rasit Onur Topaloglu | 2015-06-16 |
| 8806393 | Generation of design shapes for confining stitch-induced via structures | Rasit Onur Topaloglu | 2014-08-12 |
| 8492268 | IC having viabar interconnection and related method | Dureseti Chidambarrao, Kia-Seng Low | 2013-07-23 |
| 8484586 | System and method of predicting problematic areas for lithography in a circuit design | Timothy A. Brunner, Bernhard R. Liegl, Hua Xiang | 2013-07-09 |
| 8299622 | IC having viabar interconnection and related method | Dureseti Chidambarrao, Kia-Seng Low | 2012-10-30 |
| 8239789 | System and method of predicting problematic areas for lithography in a circuit design | Timothy A. Brunner, Bernhard R. Liegl, Hua Xiang | 2012-08-07 |
| 8117568 | Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design | Hua Xiang, Laertis Economikos, Mohammed Fazil Fayaz, Patricia A. O'Neil, Ruchir Puri | 2012-02-14 |
| 8053862 | Integrated circuit fuse | — | 2011-11-08 |
| 8001495 | System and method of predicting problematic areas for lithography in a circuit design | Timothy A. Brunner, Bernhard R. Liegl, Hua Xiang | 2011-08-16 |