Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8117568 | Apparatus, method and computer program product for fast simulation of manufacturing effects during integrated circuit design | Hua Xiang, Laertis Economikos, Mohammed Fazil Fayaz, Stephen E. Greco, Ruchir Puri | 2012-02-14 |
| 7797652 | Implementing integrated circuit yield estimation using voronoi diagrams | Michael D. Monkowski | 2010-09-14 |
| 7189644 | CMOS device integration for low external resistance | Shreesh Narasimha | 2007-03-13 |
| 6825097 | Triple oxide fill for trench isolation | Klaus D. Beyer, Deborah Ryan, Peter Smeys, Effendi Leobandung | 2004-11-30 |
| 6790733 | Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer | Wesley C. Natzle, Bruce B. Doris, Sadanand V. Deshpande, Renee T. Mo | 2004-09-14 |
| 6436823 | Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed | Cyril Cabral, Jr., Chung-Ping Eng, Lynne M. Gignac, Christian Lavoie, Kirk D. Peterson +3 more | 2002-08-20 |
| 6323130 | Method for self-aligned formation of silicide contacts using metal silicon alloys for limited silicon consumption and for reduction of bridging | Stephen Bruce Brodsky, Cyril Cabral, Jr., Roy A. Carruthers, James M. E. Harper, Christian Lavoie +1 more | 2001-11-27 |