Issued Patents All Time
Showing 26–50 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7949981 | Via density change to improve wafer surface planarity | — | 2011-05-24 |
| 7941780 | Intersect area based ground rule for semiconductor design | Albrik Avanessian, Henry A. Bonges, III, Dureseti Chidambarrao, Douglas W. Kemerer, Tina Wagner | 2011-05-10 |
| 7701035 | Laser fuse structures for high power applications | Erik L. Hedberg, Dae Young Jung, Paul S. McLaughlin, Christopher D. Muzzy, Norman J. Rohrer +1 more | 2010-04-20 |
| 7645700 | Dry etchback of interconnect contacts | Theodorus E. Standaert, William Brearley, Sujatha Sankaran | 2010-01-12 |
| 7612371 | Structure to monitor arcing in the processing steps of metal layer build on silicon-on-insulator semiconductors | Ishtiaq Ahsan, Christine Mary Bunke | 2009-11-03 |
| 7488679 | Interconnect structure and process of making the same | Theodorus E. Standaert, Pegeen M. Davis, John A. Fitzsimmons, Tze-man Ko, Naftali E. Lustig +2 more | 2009-02-10 |
| 7456501 | Semiconductor structure having recess with conductive metal | Cyprian Emeka Uzoh | 2008-11-25 |
| 7439173 | Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via | Chao-Kun Hu, Paul S. McLaughlin | 2008-10-21 |
| 7390615 | Integrated circuit fuse and method of opening | — | 2008-06-24 |
| 7368302 | Dynamic metal fill for correcting non-planar region | — | 2008-05-06 |
| 7323410 | Dry etchback of interconnect contacts | Theodorus E. Standaert, William Brearley, Sujatha Sankaran | 2008-01-29 |
| 7300825 | Customizing back end of the line interconnects | Nancy Anne Greco, Erik L. Hedberg | 2007-11-27 |
| 7301236 | Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via | Chao-Kun Hu, Paul S. McLaughlin | 2007-11-27 |
| 7253098 | Maintaining uniform CMP hard mask thickness | Shyng-Tsong Chen, Kaushik A. Kumar, Shom Ponoth, Terry A. Spooner, David L. Rath +1 more | 2007-08-07 |
| 7135398 | Reliable low-k interconnect structure with hybrid dielectric | John A. Fitzsimmons, Jia Lee, Stephen M. Gates, Terry A. Spooner, Matthew S. Angyal +3 more | 2006-11-14 |
| 7101784 | Method to generate porous organic dielectric | Lawrence A. Clevenger, Keith Kwietniak, Soon-Cheon Seo, Chih-Chao Yang, Yun-Yu Wang +1 more | 2006-09-05 |
| 7071099 | Forming of local and global wiring for semiconductor product | Theodorus E. Standaert | 2006-07-04 |
| 6921978 | Method to generate porous organic dielectric | Lawrence A. Clevenger, Keith Kwietniak, Soon-Cheon Seo, Chih-Chao Yang, Yun-Yu Wang +1 more | 2005-07-26 |
| 6917108 | Reliable low-k interconnect structure with hybrid dielectric | John A. Fitzsimmons, Jia Lee, Stephen M. Gates, Terry A. Spooner, Matthew S. Angyal +3 more | 2005-07-12 |
| 6831364 | Method for forming a porous dielectric material layer in a semiconductor device and device formed | Timothy J. Dalton, Jeffrey Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Kenneth P. Rodbell +1 more | 2004-12-14 |
| 6784105 | Simultaneous native oxide removal and metal neutral deposition method | Chih-Chao Yang, Yun-Yu Wang, Larry Clevenger, Andrew H. Simon, Kaushik Chanda +3 more | 2004-08-31 |
| 6734096 | Fine-pitch device lithography using a sacrificial hardmask | Timothy J. Dalton, Minakshisundaran Balasubramanian Anand, Michael D. Armacost, Shyng-Tsong Chen, Stephen M. Gates +2 more | 2004-05-11 |
| 6727589 | Dual damascene flowable oxide insulation structure and metallic barrier | John P. Hummel, Joyce C. Liu, Vincent J. McGahay, Rebecca D. Mih, Kamalesh K. Srivastava | 2004-04-27 |
| 6573606 | Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect | Carlos J. Sambucetti, Xiaomeng Chen, Soon-Cheon Seo, Birenda Nath Agarwala, Chao-Kun Hu +1 more | 2003-06-03 |
| 6479884 | Interim oxidation of silsesquioxane dielectric for dual damascene process | Robert Cook, John P. Hummel, Joyce C. Liu, Vincent J. McGahay, Rebecca D. Mih +1 more | 2002-11-12 |