Issued Patents All Time
Showing 1–25 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11244917 | Multilayer pillar for reduced stress interconnect and method of making same | Virendra R. Jadhav, Krystyna W. Semkow, Brian R. Sundlof | 2022-02-08 |
| 11171102 | Multilayer pillar for reduced stress interconnect and method of making same | Virendra R. Jadhav, Krystyna W. Semkow, Brian R. Sundlof | 2021-11-09 |
| 11094657 | Multilayer pillar for reduced stress interconnect and method of making same | Virendra R. Jadhav, Krystyna W. Semkow, Brian R. Sundlof | 2021-08-17 |
| 10403590 | Multilayer pillar for reduced stress interconnect and method of making same | Virendra R. Jadhav, Krystyna W. Semkow, Brian R. Sundlof | 2019-09-03 |
| 10396051 | Multilayer pillar for reduced stress interconnect and method of making same | Virendra R. Jadhav, Krystyna W. Semkow, Brian R. Sundlof | 2019-08-27 |
| 9640501 | Multilayer pillar for reduced stress interconnect and method of making same | Virendra R. Jadhav, Krystyna W. Semkow, Brian R. Sundlof | 2017-05-02 |
| 9472520 | Multilayer pillar for reduced stress interconnect and method of making same | Virendra R. Jadhav, Krystyna W. Semkow, Brian R. Sundlof | 2016-10-18 |
| 9111816 | Multilayer pillar for reduced stress interconnect and method of making same | Virendra R. Jadhav, Krystyna W. Semkow, Brian R. Sundlof | 2015-08-18 |
| 8910853 | Additives for grain fragmentation in Pb-free Sn-based solder | Charles L. Arvin, Alexandre Blander, Peter J. Brofman, Donald W. Henderson, Gareth G. Hougham +7 more | 2014-12-16 |
| 8493746 | Additives for grain fragmentation in Pb-free Sn-based solder | Charles L. Arvin, Alexandre Blander, Peter J. Brofman, Donald W. Henderson, Gareth G. Hougham +7 more | 2013-07-23 |
| 8314500 | Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers | Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith +8 more | 2012-11-20 |
| 8293587 | Multilayer pillar for reduced stress interconnect and method of making same | Virendra R. Jadhav, Krystyna W. Semkow, Brian R. Sundlof | 2012-10-23 |
| 8197612 | Optimization of metallurgical properties of a solder joint | James A. Busby, Minhua Lu, Valerie Oberson, Eric D. Perfecto, Brian R. Sundlof +2 more | 2012-06-12 |
| 7952207 | Flip-chip assembly with organic chip carrier having mushroom-plated solder resist opening | Virendra R. Jadhav, Jayshree Shah | 2011-05-31 |
| 7932169 | Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers | Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Jonathan H. Griffith +8 more | 2011-04-26 |
| 7784669 | Method and process for reducing undercooling in a lead-free tin-rich solder alloy | Gareth G. Hougham, Sung Kwon Kang, Da-Yuan Shih, Brian R. Sundlof, S. Jay Chey +4 more | 2010-08-31 |
| 7767575 | Forming robust solder interconnect structures by reducing effects of seed layer underetching | Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quinn, William E. Sablinski +3 more | 2010-08-03 |
| 7703661 | Method and process for reducing undercooling in a lead-free tin-rich solder alloy | Gareth G. Hougham, Sung Kwon Kang, Da-Yuan Shih, Brian R. Sundlof, S. Jay Chey +4 more | 2010-04-27 |
| 7572726 | Method of forming a bond pad on an I/C chip and resulting structure | Julie C. Biggs, Tien-Jen Cheng, David E. Eichstadt, Lisa A. Fanti, Jonathan H. Griffith +6 more | 2009-08-11 |
| 7473997 | Method for forming robust solder interconnect structures by reducing effects of seed layer underetching | Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon, William E. Sablinski +3 more | 2009-01-06 |
| 7425278 | Process of etching a titanium/tungsten surface and etchant used therein | Krystyna W. Semkow, Anurag Jain | 2008-09-16 |
| 7144490 | Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer | Tien-Jen Cheng, David E. Eichstadt, Jonathan H. Griffith, Sarah H. Knickerbocker, Rosemary A. Previti-Kelly +2 more | 2006-12-05 |
| 6995084 | Method for forming robust solder interconnect structures by reducing effects of seed layer underetching | Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon, William E. Sablinski +3 more | 2006-02-07 |
| 6995475 | I/C chip suitable for wire bonding | Julie C. Biggs, Tien-Jen Cheng, David E. Eichstadt, Lisa A. Fanti, Jonathan H. Griffith +6 more | 2006-02-07 |
| 6727589 | Dual damascene flowable oxide insulation structure and metallic barrier | Stephen E. Greco, John P. Hummel, Joyce C. Liu, Vincent J. McGahay, Rebecca D. Mih | 2004-04-27 |