Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10049909 | Wafer handler and methods of manufacture | John J. Garant, Brittany L. Hedrick, Edmund J. Sprogis | 2018-08-14 |
| 9613842 | Wafer handler and methods of manufacture | John J. Garant, Brittany L. Hedrick, Edmund J. Sprogis | 2017-04-04 |
| 8807184 | Reduction of edge chipping during wafer handling | Sarah H. Knickerbocker | 2014-08-19 |
| 8753460 | Reduction of edge chipping during wafer handling | Sarah H. Knickerbocker | 2014-06-17 |
| 8314500 | Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers | Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Donald W. Henderson +8 more | 2012-11-20 |
| 7932169 | Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers | Luc Belanger, Stephen L. Buchwalter, Leena Paivikki Buchwalter, Ajay P. Giri, Donald W. Henderson +8 more | 2011-04-26 |
| 7767575 | Forming robust solder interconnect structures by reducing effects of seed layer underetching | Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quinn +3 more | 2010-08-03 |
| 7572726 | Method of forming a bond pad on an I/C chip and resulting structure | Julie C. Biggs, Tien-Jen Cheng, David E. Eichstadt, Lisa A. Fanti, Randolph F. Knarr +6 more | 2009-08-11 |
| 7473997 | Method for forming robust solder interconnect structures by reducing effects of seed layer underetching | Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon +3 more | 2009-01-06 |
| 7144490 | Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer | Tien-Jen Cheng, David E. Eichstadt, Sarah H. Knickerbocker, Rosemary A. Previti-Kelly, Roger A. Quon +2 more | 2006-12-05 |
| 6995084 | Method for forming robust solder interconnect structures by reducing effects of seed layer underetching | Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, Roger A. Quon +3 more | 2006-02-07 |
| 6995475 | I/C chip suitable for wire bonding | Julie C. Biggs, Tien-Jen Cheng, David E. Eichstadt, Lisa A. Fanti, Randolph F. Knarr +6 more | 2006-02-07 |
| 6992389 | Barrier for interconnect and method | Panayotis Andricacos, Tien-Jen Cheng, Emanuel I. Cooper, David E. Eichstadt, Randolph F. Knarr +2 more | 2006-01-31 |
| 6531069 | Reactive Ion Etching chamber design for flip chip interconnections | Kamalesh K. Srivastava, Peter C. Wade, William Brearley | 2003-03-11 |
| 6293457 | Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization | Kamalesh K. Srivastava, Mary Cullinan-Scholl, William Brearley, Peter C. Wade | 2001-09-25 |
| 6228665 | Method of measuring oxide thickness during semiconductor fabrication | Ronald L. Smith, Roger L. Verkuil | 2001-05-08 |
| 5277749 | Methods and apparatus for relieving stress and resisting stencil delamination when performing lift-off processes that utilize high stress metals and/or multiple evaporation steps | John I. Kim, Thomas L. Leong, William J. Tilly, Sari Wacks | 1994-01-11 |
| 4588471 | Process for etching composite chrome layers | Everton H. Henriques, James L. Kehoe, III, Marshall J. Suskie | 1986-05-13 |