Issued Patents All Time
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12334461 | Bonding structure using two oxide layers with different stress levels, and related method | Jorge A. Lubguban, Lloyd Burrell, John J. Garant, Matthew C. Gorfien | 2025-06-17 |
| 11502106 | Multi-layered substrates of semiconductor devices | Benjamin V. Fasano, Koushik Ramachandran, Ian Melville, Jorge A. Lubguban | 2022-11-15 |
| 10520679 | Fiber alignment to photonics chip | Jorge A. Lubguban, Tracy A. Tong | 2019-12-31 |
| 10090255 | Dicing channels for glass interposers | Brittany L. Hedrick, Vijay Sukumaran, Christopher L. Tessler, Richard F. Indyk | 2018-10-02 |
| 9401336 | Dual layer stack for contact formation | Charles L. Arvin, Harry D. Cox, Brian M. Erwin, Karen P. McLaughlin, David J. Russell | 2016-07-26 |
| 9362223 | Integrated circuit assembly with cushion polymer layer | Paul S. Andry, Ron R. Legario, Cornelia K. Tsang, Melvin P. Zussman | 2016-06-07 |
| 9209128 | Integrated circuit assembly with cushion polymer layer | Paul S. Andry, Ron R. Legario, Cornelia K. Tsang, Melvin P. Zussman | 2015-12-08 |
| 9171749 | Handler wafer removal facilitated by the addition of an amorphous carbon layer on the handler wafer | Bing Dang, Douglas C. La Tulipe, Jr., Spyridon Skordas, Cornelia K. Tsang, Kevin R. Winstel | 2015-10-27 |
| 8807184 | Reduction of edge chipping during wafer handling | Jonathan H. Griffith | 2014-08-19 |
| 8753460 | Reduction of edge chipping during wafer handling | Jonathan H. Griffith | 2014-06-17 |
| 8668834 | Protecting a mold having a substantially planar surface provided with a plurality of mold cavities | Bradley P. Jones, Richard P. Volant | 2014-03-11 |
| 7999377 | Method and structure for optimizing yield of 3-D chip manufacture | Edward M. DeMulder, Michael J. Shapiro, Albert M. Young | 2011-08-16 |
| 7833897 | Process for making interconnect solder Pb-free bumps free from organo-tin/tin deposits on the wafer surface | Sean A. Allen, John J. Garant, Jerry A. Gorrell, Phillip W. Palmatier, Christopher L. Tessler | 2010-11-16 |
| 7767575 | Forming robust solder interconnect structures by reducing effects of seed layer underetching | Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Roger A. Quinn, William E. Sablinski +3 more | 2010-08-03 |
| 7737003 | Method and structure for optimizing yield of 3-D chip manufacture | Edward M. DeMulder, Michael J. Shapiro, Albert M. Young | 2010-06-15 |
| 7666780 | Alignment verification for C4NP solder transfer | Jerry A. Gorrell, Srinivasa S. N. Reddy | 2010-02-23 |
| 7572726 | Method of forming a bond pad on an I/C chip and resulting structure | Julie C. Biggs, Tien-Jen Cheng, David E. Eichstadt, Lisa A. Fanti, Jonathan H. Griffith +6 more | 2009-08-11 |
| 7473997 | Method for forming robust solder interconnect structures by reducing effects of seed layer underetching | Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Roger A. Quon, William E. Sablinski +3 more | 2009-01-06 |
| 7144490 | Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer | Tien-Jen Cheng, David E. Eichstadt, Jonathan H. Griffith, Rosemary A. Previti-Kelly, Roger A. Quon +2 more | 2006-12-05 |
| 6995475 | I/C chip suitable for wire bonding | Julie C. Biggs, Tien-Jen Cheng, David E. Eichstadt, Lisa A. Fanti, Jonathan H. Griffith +6 more | 2006-02-07 |
| 6995084 | Method for forming robust solder interconnect structures by reducing effects of seed layer underetching | Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Roger A. Quon, William E. Sablinski +3 more | 2006-02-07 |
| 6661100 | Low impedance power distribution structure for a semiconductor chip package | Brent A. Anderson, Randolph F. Knarr, Edmund J. Sprogis, Kamalesh K. Srivastava | 2003-12-09 |
| 6335210 | Baseplate for chip burn-in and/of testing, and method thereof | Mukta S. Farooq, Raymond A. Jackson, Sudipta K. Ray | 2002-01-01 |
| 6284574 | Method of producing heat dissipating structure for semiconductor devices | Kevin S. Petrarca, Joyce C. Liu, Rebecca D. Mih | 2001-09-04 |
| 5946552 | Universal cost reduced substrate structure method and apparatus | Kenneth A. Bird, Myra Muth Boenke, Jason L. Frankel, Ahmed Sayeed Shah | 1999-08-31 |