LB

Lloyd Burrell

IBM: 9 patents #11,918 of 70,183Top 20%
GU Globalfoundries U.S.: 1 patents #344 of 665Top 55%
Infineon Technologies Ag: 1 patents #4,439 of 7,486Top 60%
Overall (All Time): #483,368 of 4,157,543Top 15%
10
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12334461 Bonding structure using two oxide layers with different stress levels, and related method Jorge A. Lubguban, Sarah H. Knickerbocker, John J. Garant, Matthew C. Gorfien 2025-06-17
7867820 Methods for forming co-planar wafer-scale chip packages Howard H. Chen, Louis L. Hsu, Wolfgang Sauter 2011-01-11
7405108 Methods for forming co-planar wafer-scale chip packages Howard H. Chen, Louis L. Hsu, Wolfgang Sauter 2008-07-29
7294565 Method of fabricating a wire bond pad with Ni/Au metallization Charles R. Davis, Ronald D. Goldblatt, William Francis Landers, Sanjay C. Mehta 2007-11-13
7250311 Wirebond crack sensor for low-k die Toyohiro Aoki, Wolfgang Sauter 2007-07-31
7087997 Copper to aluminum interlayer interconnect using stud and via liner Edward E. Cooney, III, Jeffrey P. Gambino, John E. Heidenreich, III, Hyun Koo Lee, Mark D. Levy +6 more 2006-08-08
7037824 Copper to aluminum interlayer interconnect using stud and via liner Edward E. Cooney, III, Jeffrey P. Gambino, John E. Heidenreich, III, Hyun Koo Lee, Mark D. Levy +6 more 2006-05-02
6960831 Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad Kwong Hon Wong, Adreanne Kelly, Samuel McKnight 2005-11-01
6908841 Support structures for wirebond regions of contact pads over low modulus materials Douglas W. Kemerer, Henry A. Nye, III, Hans-Joachim Barth, Emmanuel F. Crabbe, David F. Anderson +1 more 2005-06-21
6559042 Process for forming fusible links Hans-Joachim Barth, Gerald Friese, Michael Stetter 2003-05-06