Issued Patents All Time
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7767575 | Forming robust solder interconnect structures by reducing effects of seed layer underetching | Kamalesh K. Srivastava, Subhash L. Shinde, Tien-Jen Cheng, Sarah H. Knickerbocker, William E. Sablinski +3 more | 2010-08-03 |