Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8247905 | Formation of vertical devices by electroplating | Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw, Mary B. Rothwell | 2012-08-21 |
| 7803639 | Method of forming vertical contacts in integrated circuits | Solomon Assefa, Michael C. Gaidis, Sivananda K. Kanakasabapathy | 2010-09-28 |
| 7608538 | Formation of vertical devices by electroplating | Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw, Mary B. Rothwell | 2009-10-27 |
| 7531367 | Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit | Solomon Assefa, Michael C. Gaidis, Sivananda K. Kanakasabapathy, David W. Abraham | 2009-05-12 |
| 7097777 | Magnetic switching device | Gregory Costrini, George Stojakovic, Kia-Seng Low | 2006-08-29 |
| 7087438 | Encapsulation of conductive lines of semiconductor devices | Ihar Kasko, Kia-Seng Low | 2006-08-08 |
| 6985384 | Spacer integration scheme in MRAM technology | Gregory Costrini, Kia-Seng Low, Igor Kasko, Frank Findeis, Wolfgang Raberg | 2006-01-10 |
| 6933204 | Method for improved alignment of magnetic tunnel junction elements | Chandrasekhar Sarma, Sivananda K. Kanakasabapathy, Ihar Kasko, Greg Costrini, Michael C. Gaidis | 2005-08-23 |
| 6743642 | Bilayer CMP process to improve surface roughness of magnetic stack in MRAM technology | Gregory Costrini, Kia-Seng Low, Mahadevaiyer Krishnan | 2004-06-01 |
| 6727589 | Dual damascene flowable oxide insulation structure and metallic barrier | Stephen E. Greco, Joyce C. Liu, Vincent J. McGahay, Rebecca D. Mih, Kamalesh K. Srivastava | 2004-04-27 |
| 6680500 | Insulating cap layer and conductive cap layer for semiconductor devices with magnetic material layers | Kia-Seng Low, Igor Kasko, Gregory Costrini | 2004-01-20 |
| 6593660 | Plasma treatment to enhance inorganic dielectric adhesion to copper | Leena Paivikki Buchwalter, Barbara Luther, Paul D. Agnello, Terence L. Kane, Dirk Manger +3 more | 2003-07-15 |
| 6577011 | Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same | Leena Paivikki Buchwalter, Alessandro C. Callegari, Stephan A. Cohen, Teresita O. Graham, Christopher V. Jahnes +3 more | 2003-06-10 |
| 6551924 | Post metalization chem-mech polishing dielectric etch | Timothy J. Dalton | 2003-04-22 |
| 6479884 | Interim oxidation of silsesquioxane dielectric for dual damascene process | Robert Cook, Stephen E. Greco, Joyce C. Liu, Vincent J. McGahay, Rebecca D. Mih +1 more | 2002-11-12 |
| 6448176 | Dual damascene processing for semiconductor chip interconnects | Alfred Grill, Christopher V. Jahnes, Vishnubhai V. Patel, Katherine L. Saenger | 2002-09-10 |
| 6423566 | Moisture and ion barrier for protection of devices and interconnect structures | Claudius Feger | 2002-07-23 |
| 6348736 | In situ formation of protective layer on silsesquioxane dielectric for dual damascene process | Vincent J. McGahay, Joyce C. Liu, Rebecca D. Mih, Kamalesh K. Srivastava, Robert Cook +1 more | 2002-02-19 |
| 6329280 | Interim oxidation of silsesquioxane dielectric for dual damascene process | Robert Cook, Stephen E. Greco, Joyce C. Liu, Vincent J. McGahay, Rebecca D. Mih +1 more | 2001-12-11 |
| 6261951 | Plasma treatment to enhance inorganic dielectric adhesion to copper | Leena Paivikki Buchwalter, Barbara Luther, Paul D. Agnello, Terence L. Kane, Dirk Manger +3 more | 2001-07-17 |
| 6255217 | Plasma treatment to enhance inorganic dielectric adhesion to copper | Paul D. Agnello, Leena Paivikki Buchwalter, Barbara Luther, Anthony K. Stamper | 2001-07-03 |
| 6221780 | Dual damascene flowable oxide insulation structure and metallic barrier | Stephen E. Greco, Joyce C. Liu, Vincent J. McGahay, Rebecca D. Mih, Kamalesh K. Srivastava | 2001-04-24 |
| 6184121 | Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same | Leena Paivikki Buchwalter, Alessandro C. Callegari, Stephan A. Cohen, Teresita O. Graham, Christopher V. Jahnes +3 more | 2001-02-06 |
| 6140226 | Dual damascene processing for semiconductor chip interconnects | Alfred Grill, Christopher V. Jahnes, Vishnubhai V. Patel, Katherine L. Saenger | 2000-10-31 |
| 6130472 | Moisture and ion barrier for protection of devices and interconnect structures | Claudius Feger | 2000-10-10 |