Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9105747 | Tunable stressed polycrystalline silicon on dielectrics in an integrated circuit | Matthias Hierlemann | 2015-08-11 |
| 8846462 | Transistor level routing | Martin Ostermayr | 2014-09-30 |
| 8715909 | Lithography systems and methods of manufacturing using thereof | Alois Gutmann, Henning Haffner, Sajan Marokkey, Roderick Koehle | 2014-05-06 |
| 8492079 | Method of forming a pattern of an array of shapes including a blocked region | Chia-Chen Chen, Wu-Song Huang, Wai-Kin Li | 2013-07-23 |
| 8394574 | Metrology systems and methods for lithography processes | Jingyu Lian, Matthias Lipinski, Haoren Zhuang | 2013-03-12 |
| 8377800 | Alignment marks for polarized light lithography and method for use thereof | Sajan Marokkey, Alois Gutmann | 2013-02-19 |
| 8359562 | System and method for semiconductor device fabrication using modeling | Todd C. Bailey | 2013-01-22 |
| 8349528 | Semiconductor devices and methods of manufacturing thereof | Matthias Lipinski, Alois Gutmann, Jingyu Lian, Haoren Zhuang | 2013-01-08 |
| 8183129 | Alignment marks for polarized light lithography and method for use thereof | Sajan Marokkey, Alois Gutmann | 2012-05-22 |
| 8071261 | Lithography masks and methods of manufacture thereof | Alois Gutmann, Sajan Marokkey, Henning Haffner, Haoren Zhuang, Matthias Lipinski | 2011-12-06 |
| 8067135 | Metrology systems and methods for lithography processes | Jingyu Lian, Matthias Lipinski, Haoren Zhuang | 2011-11-29 |
| 8063406 | Semiconductor device having a polysilicon layer with a non-constant doping profile | Haoren Zhuang, Matthias Lipinski, Jingyu Lian | 2011-11-22 |
| 8007985 | Semiconductor devices and methods of manufacturing thereof | Matthias Lipinski, Alois Gutmann, Jingyu Lian, Haoren Zhuang | 2011-08-30 |
| 7947431 | Lithography masks and methods of manufacture thereof | Alois Gutmann, Henning Haffner, Sajan Marokkey, Josef Maynollo | 2011-05-24 |
| 7863130 | Tunable stressed polycrystalline silicon on dielectrics in an integrated circuit | Matthias Hierlemann | 2011-01-04 |
| 7842579 | Method for manufacturing a semiconductor device having doped and undoped polysilicon layers | Haoren Zhuang, Matthias Lipinski, Jingyu Lian | 2010-11-30 |
| 7799486 | Lithography masks and methods of manufacture thereof | Alois Gutmann, Henning Haffner, Sajan Marokkey, Josef Maynollo | 2010-09-21 |
| 7794903 | Metrology systems and methods for lithography processes | Jingyu Lian, Matthias Lipinski, Haoren Zhuang | 2010-09-14 |
| 7713824 | Small feature integrated circuit fabrication | Alois Gutmann, Sajan Marokkey, Josef Maynollo | 2010-05-11 |
| 7687925 | Alignment marks for polarized light lithography and method for use thereof | Sajan Marokkey, Alois Gutmann | 2010-03-30 |
| 7674350 | Feature dimension control in a manufacturing process | Haoren Zhuang, Alois Gutmann, Matthias Lipinski, Jingyu Lian | 2010-03-09 |
| 7666800 | Feature patterning methods | Sajan Marokkey, Alois Gutmann, Klaus Herold | 2010-02-23 |
| 7442624 | Deep alignment marks on edge chips for subsequent alignment of opaque layers | Ihar Kasko | 2008-10-28 |
| 7223612 | Alignment of MTJ stack to conductive lines in the absence of topography | — | 2007-05-29 |
| 6933204 | Method for improved alignment of magnetic tunnel junction elements | Sivananda K. Kanakasabapathy, Ihar Kasko, Greg Costrini, John P. Hummel, Michael C. Gaidis | 2005-08-23 |