Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11847398 | Automatic generation of ground rule verification macros | Shruthi Venkateshan, Tenko Yamashita, Jinning Liu | 2023-12-19 |
| 9070759 | Semiconductor device and method of making same | Jin-Ping Han, Haoren Zhuang, Jiang Yan, Manfred Eller | 2015-06-30 |
| 8697339 | Semiconductor device manufacturing methods | Haoren Zhuang, Chong-Kwang Chang, Alois Gutmann, Matthias Lipinski, Len Yuan Tsou +1 more | 2014-04-15 |
| 8394574 | Metrology systems and methods for lithography processes | Chandrasekhar Sarma, Matthias Lipinski, Haoren Zhuang | 2013-03-12 |
| 8349528 | Semiconductor devices and methods of manufacturing thereof | Matthias Lipinski, Alois Gutmann, Chandrasekhar Sarma, Haoren Zhuang | 2013-01-08 |
| 8138055 | Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same | Jin-Ping Han, Alois Gutmann, Roman Knoefler, Jiang Yan, Chris Stapelmann +1 more | 2012-03-20 |
| 8067135 | Metrology systems and methods for lithography processes | Chandrasekhar Sarma, Matthias Lipinski, Haoren Zhuang | 2011-11-29 |
| 8063406 | Semiconductor device having a polysilicon layer with a non-constant doping profile | Haoren Zhuang, Matthias Lipinski, Chandrasekhar Sarma | 2011-11-22 |
| 8007985 | Semiconductor devices and methods of manufacturing thereof | Matthias Lipinski, Alois Gutmann, Chandrasekhar Sarma, Haoren Zhuang | 2011-08-30 |
| 7842579 | Method for manufacturing a semiconductor device having doped and undoped polysilicon layers | Haoren Zhuang, Matthias Lipinski, Chandrasekhar Sarma | 2010-11-30 |
| 7800182 | Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same | Jin-Ping Han, Alois Gutmann, Roman Knoefler, Jiang Yan, Chris Stapelmann +1 more | 2010-09-21 |
| 7794903 | Metrology systems and methods for lithography processes | Chandrasekhar Sarma, Matthias Lipinski, Haoren Zhuang | 2010-09-14 |
| 7745292 | Method for fabricating a semiconductor gate structure | Jong-Pyo Kim | 2010-06-29 |
| 7674350 | Feature dimension control in a manufacturing process | Haoren Zhuang, Alois Gutmann, Matthias Lipinski, Chandrasekhar Sarma | 2010-03-09 |
| 7586158 | Piezoelectric stress liner for bulk and SOI | Matthias Hierlemann, Rudolf Stierstorfer | 2009-09-08 |
| 7378700 | Self-aligned V0-contact for cell size reduction | Nicolas Nagel, Stefan Gernhardt, Rainer Bruchhaus, Andreas Hilliger, Uwe Wellhausen | 2008-05-27 |
| 7319270 | Multi-layer electrode and method of forming the same | Chenting Lin, Nicolas Nagel, Michael Wise | 2008-01-15 |
| 7270884 | Adhesion layer for Pt on SiO2 | Kwong Hon Wong, Michael Wise, Young Limb, Nicolas Nagel | 2007-09-18 |
| 7061035 | Self-aligned V0-contact for cell size reduction | Nicolas Nagel, Stefan Gernhardt, Rainer Bruchhaus, Andreas Hilliger, Uwe Wellhausen | 2006-06-13 |
| 7042705 | Sidewall structure and method of fabrication for reducing oxygen diffusion to contact plugs during CW hole reactive ion etch processing | Haoren Zhuang, Ulrich Egger, Kazuhiro Tomioka, Nicolas Nagel, Andreas Hilliger +1 more | 2006-05-09 |
| 7001780 | Method of fabrication of an FeRAM capacitor and an FeRAM capacitor formed by the method | Haoren Zhuang, Ulrich Egger, Stefan Gernhardt, Hiroyuki Kanaya | 2006-02-21 |
| 6984555 | Device and method for inhibiting oxidation of contact plugs in ferroelectric capacitor devices | — | 2006-01-10 |
| 6897501 | Avoiding shorting in capacitors | Haoren Zhuang, Ulrich Egger, Gerhard Beitel, Karl Hornik | 2005-05-24 |
| 6839220 | Multi-layer barrier allowing recovery anneal for ferroelectric capacitors | Andreas Hilliger, Nicolas Nagel, Rainer Bruchhaus, Stefan Gernhardt, Uwe Wellhausen +2 more | 2005-01-04 |
| 6794705 | Multi-layer Pt electrode for DRAM and FRAM with high K dielectric materials | Chenting Lin, Nicolas Nagel, Michael Wise | 2004-09-21 |