Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8697339 | Semiconductor device manufacturing methods | Haoren Zhuang, Chong-Kwang Chang, Alois Gutmann, Jingyu Lian, Matthias Lipinski +1 more | 2014-04-15 |
| 8219938 | Semiconductor inter-field dose correction | Hyung-Rae Lee, Dong-Hee Yu, Haoren Zhuang | 2012-07-10 |
| 7759235 | Semiconductor device manufacturing methods | Haoren Zhuang, Helen Wang, Scott D. Halle | 2010-07-20 |
| 7541290 | Methods of forming mask patterns on semiconductor wafers that compensate for nonuniform center-to-edge etch rates during photolithographic processing | Chong-Kwang Chang, Wan Jae Park, Haoren Zhuang, Matthias Lipinsky, Shailendra Mishra | 2009-06-02 |
| 6960510 | Method of making sub-lithographic features | Sadanand V. Deshpande, Toshiharu Furukawa, David V. Horak, Wesley C. Natzle, Akihisa Sekiguchi +1 more | 2005-11-01 |
| 6884734 | Vapor phase etch trim structure with top etch blocking layer | Frederick Buehrer, Derek Chen, William Chu, Scott W. Crowder, Sadanand V. Deshpande +4 more | 2005-04-26 |
| 6864041 | Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching | Jeffrey J. Brown, Sadanand V. Deshpande, David V. Horak, Maheswaran Surendra, Qingyun Yang +2 more | 2005-03-08 |
| 6828187 | Method for uniform reactive ion etching of dual pre-doped polysilicon regions | Joyce C. Liu, Qingyun Yang | 2004-12-07 |
| 6703269 | Method to form gate conductor structures of dual doped polysilicon | Jeffrey J. Brown, Qingyun Yang | 2004-03-09 |
| 6528363 | Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch | Victor Ku, Maheswaran Surendra, Ying Zhang | 2003-03-04 |
| 6509219 | Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch | Hongwen Yan, Qingyun Yang, Chienfan Yu | 2003-01-21 |
| 6328041 | Universal cleaning wafer for a plasma chamber | Jeffrey J. Brown, Christopher N. Collins, Wilson Tong Lee, George A. Kaplita, Stefan Schmitz | 2001-12-11 |
| 5606521 | Electrically erasable and programmable read only memory with non-uniform dielectric thickness | Di-Son Kuo, Satyendranath Mukherjee, Mark Simpson | 1997-02-25 |
| 5240875 | Selective oxidation of silicon trench sidewall | — | 1993-08-31 |
| 5146426 | Electrically erasable and programmable read only memory with trench structure | Satyendranath Mukherjee, Di-Son Kuo | 1992-09-08 |