VK

Victor Ku

IBM: 15 patents #7,450 of 70,183Top 15%
Applied Materials: 1 patents #4,780 of 7,310Top 70%
PE Philips Electronics: 1 patents #6 of 39Top 20%
VT Vlsi Technology: 1 patents #349 of 594Top 60%
Overall (All Time): #258,952 of 4,157,543Top 7%
18
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7655557 CMOS silicide metal gate integration Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub Kedzierski +6 more 2010-02-02
7635648 Methods for fabricating dual material gate in a semiconductor device Igor Peidous, Joe Piccirillo 2009-12-22
7411227 CMOS silicide metal gate integration Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub Kedzierski +6 more 2008-08-12
7326610 Process options of forming silicided metal gates for advanced CMOS devices Ricky S. Amos, Douglas A. Buchanan, Cyril Cabral, Jr., Evgeni Gousev, An Steegen 2008-02-05
7056794 FET gate structure with metal gate electrode and silicide contact An Steegen, Hsing-Jen Wann 2006-06-06
7056782 CMOS silicide metal gate integration Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub Kedzierski +6 more 2006-06-06
7041538 Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS Meikei Ieong, Omer H. Dokumaci, Thomas S. Kanarsky 2006-05-09
7029966 Process options of forming silicided metal gates for advanced CMOS devices Ricky S. Amos, Douglas A. Buchanan, Cyril Cabral, Jr., Evgeni Gousev, An Steegen 2006-04-18
6974736 Method of forming FET silicide gate structures incorporating inner spacers An Steegen, Hsing-Jen Wann, Keith Kwong Hon Wong 2005-12-13
6927117 Method for integration of silicide contacts and silicide gate metals Cyril Cabral, Jr., Jakub Kedzierski, Christian Lavoie, Vijay Narayanan, An Steegen 2005-08-09
6921711 Method for forming metal replacement gate of high performance Cyril Cabral, Jr., Paul C. Jamison, Ying Li, Vijay Narayanan, An Steegen +2 more 2005-07-26
6677646 Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS Meikei Ieong, Omer H. Dokumaci, Thomas S. Kanarsky 2004-01-13
6544874 Method for forming junction on insulator (JOI) structure Jack A. Mandelman, Kevin K. Chan, Bomy Chen, Oleg Gluschenkov, Rajarao Jammy +2 more 2003-04-08
6528363 Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etch Maheswaran Surendra, Len Yuan Tsou, Ying Zhang 2003-03-04
6506649 Method for forming notch gate having self-aligned raised source/drain structure Ka-Hing Fung, Atul Ajmera, Dominic J. Schepis 2003-01-14
6437377 Low dielectric constant sidewall spacer using notch gate process Atul Ajmera, Ka-Hing Fung, Dominic J. Schepis 2002-08-20
6383918 Method for reducing semiconductor contact resistance Delbert Parks 2002-05-07
6184119 Methods for reducing semiconductor contact resistance Delbert Parks 2001-02-06