| 7928443 |
Method and structure for forming strained SI for CMOS devices |
Haining Yang, Ying Zhang |
2011-04-19 |
$4,236,000 |
| 7923786 |
Selective silicon-on-insulator isolation structure and method |
Maheswaran Surendra, Hsing-Jen Wann, Ying Zhang, Franz Zach, Robert C. Wong |
2011-04-12 |
$5,593,000 |
| 7700951 |
Method and structure for forming strained Si for CMOS devices |
Haining Yang, Ying Zhang |
2010-04-20 |
$4,962,000 |
| 7655557 |
CMOS silicide metal gate integration |
Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub Kedzierski +6 more |
2010-02-02 |
$8,575,000 |
| 7550338 |
Method and structure for forming strained SI for CMOS devices |
Haining Yang, Ying Zhang |
2009-06-23 |
$5,277,000 |
| 7429752 |
Method and structure for forming strained SI for CMOS devices |
Haining Yang, Ying Zhang |
2008-09-30 |
$13,468,000 |
| 7411227 |
CMOS silicide metal gate integration |
Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub Kedzierski +6 more |
2008-08-12 |
$8,244,000 |
| 7396714 |
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
Huajie Chen, Dureseti Chidambarrao, Oleg Gluschenkov, Haining Yang |
2008-07-08 |
$9,414,000 |
| 7326983 |
Selective silicon-on-insulator isolation structure and method |
Maheswaran Surendra, Hsing-Jen Wann, Ying Zhang, Franz Zach, Robert C. Wong |
2008-02-05 |
$10,462,000 |
| 7326610 |
Process options of forming silicided metal gates for advanced CMOS devices |
Ricky S. Amos, Douglas A. Buchanan, Cyril Cabral, Jr., Evgeni Gousev, Victor Ku |
2008-02-05 |
$10,462,000 |
| 7291528 |
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
Huajie Chen, Dureseti Chidambarrao, Oleg Gluschenkov, Haining Yang |
2007-11-06 |
$19,194,000 |
| 7129126 |
Method and structure for forming strained Si for CMOS devices |
Haining Yang, Ying Zhang |
2006-10-31 |
$4,068,000 |
| 7112481 |
Method for forming self-aligned dual salicide in CMOS technologies |
Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, John J. Ellis-Monaghan, Christian Lavoie +3 more |
2006-09-26 |
$6,900,000 |
| 7081397 |
Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow |
Christopher V. Baiocco, Ying Zhang |
2006-07-25 |
$9,389,000 |
| 7067368 |
Method for forming self-aligned dual salicide in CMOS technologies |
Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, John J. Ellis-Monaghan, Christian Lavoie +3 more |
2006-06-27 |
$5,894,000 |
| 7064025 |
Method for forming self-aligned dual salicide in CMOS technologies |
Sunfei Fang, Cyril Cabral, Jr., Chester T. Dziobkowski, John J. Ellis-Monaghan, Christian Lavoie +3 more |
2006-06-20 |
$5,983,000 |
| 7056794 |
FET gate structure with metal gate electrode and silicide contact |
Victor Ku, Hsing-Jen Wann |
2006-06-06 |
$5,053,000 |
| 7056782 |
CMOS silicide metal gate integration |
Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub Kedzierski +6 more |
2006-06-06 |
$5,053,000 |
| 7029966 |
Process options of forming silicided metal gates for advanced CMOS devices |
Ricky S. Amos, Douglas A. Buchanan, Cyril Cabral, Jr., Evgeni Gousev, Victor Ku |
2006-04-18 |
$9,074,000 |
| 6974736 |
Method of forming FET silicide gate structures incorporating inner spacers |
Victor Ku, Hsing-Jen Wann, Keith Kwong Hon Wong |
2005-12-13 |
$5,273,000 |
| 6936522 |
Selective silicon-on-insulator isolation structure and method |
Maheswaran Surendra, Hsing-Jen Wann, Ying Zhang, Franz Zach, Robert C. Wong |
2005-08-30 |
$6,623,000 |
| 6927117 |
Method for integration of silicide contacts and silicide gate metals |
Cyril Cabral, Jr., Jakub Kedzierski, Victor Ku, Christian Lavoie, Vijay Narayanan |
2005-08-09 |
$5,698,000 |
| 6921711 |
Method for forming metal replacement gate of high performance |
Cyril Cabral, Jr., Paul C. Jamison, Victor Ku, Ying Li, Vijay Narayanan +2 more |
2005-07-26 |
$7,521,000 |
| 6891192 |
Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
Huajie Chen, Dureseti Chidambarrao, Oleg Gluschenkov, Haining Yang |
2005-05-10 |
$5,425,000 |
| 6876040 |
Dense SRAM cells with selective SOI |
Hsingjen Wann, Ying Zhang, Robert C. Wong |
2005-04-05 |
$5,479,000 |
