Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7923786 | Selective silicon-on-insulator isolation structure and method | An Steegen, Maheswaran Surendra, Ying Zhang, Franz Zach, Robert C. Wong | 2011-04-12 |
| 7326983 | Selective silicon-on-insulator isolation structure and method | An Steegen, Maheswaran Surendra, Ying Zhang, Franz Zach, Robert C. Wong | 2008-02-05 |
| 7081393 | Reduced dielectric constant spacer materials integration for high speed logic gates | Michael P. Belyansky, Joyce C. Liu, Richard S. Wise, Hongwen Yan | 2006-07-25 |
| 7056794 | FET gate structure with metal gate electrode and silicide contact | Victor Ku, An Steegen | 2006-06-06 |
| 6975133 | Logic circuits having linear and cellular gate transistors | Victor Wing Chung Chan, Shih-Fen Huang, Oleg Gluschenkov | 2005-12-13 |
| 6974736 | Method of forming FET silicide gate structures incorporating inner spacers | Victor Ku, An Steegen, Keith Kwong Hon Wong | 2005-12-13 |
| 6936522 | Selective silicon-on-insulator isolation structure and method | An Steegen, Maheswaran Surendra, Ying Zhang, Franz Zach, Robert C. Wong | 2005-08-30 |
| 6653686 | Structure and method of controlling short-channel effect of very short channel MOSFET | — | 2003-11-25 |
| 6429091 | Patterned buried insulator | Bomy Chen, Alexander Hirsch, Sundar Iyer, Nivo Rovedo, Ying Zhang | 2002-08-06 |
| 6300649 | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility | Chenming Hu, Mansun Chan, Ping Keung Ko | 2001-10-09 |
| 6297127 | Self-aligned deep trench isolation to shallow trench isolation | Bomy Chen, Liang Han, Robert Hannon, Jay G. Harrington, Herbert L. Ho | 2001-10-02 |
| 6268640 | Forming steep lateral doping distribution at source/drain junctions | Heemyong Park, Yuan Taur | 2001-07-31 |
| 6121077 | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility | Chenming Hu, Mansun Chan, Ping Keung Ko | 2000-09-19 |
| 6057724 | Method and apparatus for synchronized clock distribution | — | 2000-05-02 |
| 6025242 | Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation | William H. Ma | 2000-02-15 |
| 6022771 | Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions | William H. Ma | 2000-02-08 |
| 5998248 | Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region | William H. Ma | 1999-12-07 |
| 5998273 | Fabrication of semiconductor device having shallow junctions | William H. Ma | 1999-12-07 |
| 5982003 | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility | Chenming Hu, Mansun Chan, Ping Keung Ko | 1999-11-09 |
| 5780899 | Delta doped and counter doped dynamic threshold voltage MOSFET for ultra-low voltage operation | Chenming Hu | 1998-07-14 |
| 5599728 | Method of fabricating a self-aligned high speed MOSFET device | Chenming Hu | 1997-02-04 |
| 5489792 | Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility | Chenming Hu, Mansun Chan, Ping Keung Ko | 1996-02-06 |
| 5448513 | Capacitorless DRAM device on silicon-on-insulator substrate | Chenming Hu | 1995-09-05 |