Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10964817 | (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor device | Chao-Ching Cheng, Chih-Hsin Ko | 2021-03-30 |
| 10770588 | (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor device | Chao-Ching Cheng, Chih-Hsin Ko | 2020-09-08 |
| 9406518 | (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor substrate | Chao-Ching Cheng, Chih-Hsin Ko | 2016-08-02 |
| 9105661 | Fin field effect transistor gate oxide | Gin-Chen Huang, Neng-Kuo Chen | 2015-08-11 |
| 8716863 | Structure and method for high performance interconnect | Ting-Chu Ko | 2014-05-06 |
| 8268698 | Formation of improved SOI substrates using bulk semiconductor wafers | William K. Henson, Dureseti Chidambarrao, Kern Rim, Hung Y. Ng | 2012-09-18 |
| 7932158 | Formation of improved SOI substrates using bulk semiconductor wafers | William K. Henson, Dureseti Chidambarrao, Kern Rim, Hung Y. Ng | 2011-04-26 |
| 7452784 | Formation of improved SOI substrates using bulk semiconductor wafers | William K. Henson, Dureseti Chidambarrao, Kern Rim, Hung Y. Ng | 2008-11-18 |
| 6876040 | Dense SRAM cells with selective SOI | Ying Zhang, Robert C. Wong, An Steegen | 2005-04-05 |
| 6093947 | Recessed-gate MOSFET with out-diffused source/drain extension | Hussein I. Hanafi, Young Hoon Lee | 2000-07-25 |
| 6063699 | Methods for making high-aspect ratio holes in semiconductor and its application to a gate damascene process for sub- 0.05 micron mosfets | Hussein I. Hanafi, Young Hoon Lee | 2000-05-16 |