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Spacer and process to enhance the strain in the channel with stress liner |
Christopher V. Baiocco, Xiangdong Chen, Wenzhi Gao, Young Way Teh |
2013-06-11 |
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Methods of forming semiconductor devices using embedded L-shape spacers |
Zhijiong Luo, Young Way Teh |
2010-07-20 |
| 7741165 |
Polycrystalline SiGe Junctions for advanced devices |
Kevin K. Chan, Robert J. Miller, Erin C. Jones |
2010-06-22 |
| 7387924 |
Polycrystalline SiGe junctions for advanced devices |
Kevin K. Chan, Robert J. Miller, Erin C. Jones |
2008-06-17 |
| 7135391 |
Polycrystalline SiGe junctions for advanced devices |
Kevin K. Chan, Rober J. Miller, Erin C. Jones |
2006-11-14 |
| 7091128 |
Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs |
Andres Bryant, Percy V. Gilbert, Michael A. Gribelyuk, Edward P. Maciejewski, Renee T. Mo +1 more |
2006-08-15 |
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Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs |
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2006-01-31 |
| 6900092 |
Surface engineering to prevent epi growth on gate poly during selective epi processing |
Dominic J. Schepis, Michael D. Steigerwalt |
2005-05-31 |
| 6642156 |
Method for forming heavy nitrogen-doped ultra thin oxynitride gate dielectrics |
Evgeni Gousev, Christopher P. D'Emic |
2003-11-04 |
| 6605521 |
Method of forming an oxide film on a gate side wall of a gate structure |
Karanam Balasubramanyam, Tomio Katata, Shang-Bin Ko |
2003-08-12 |
| 6602759 |
Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon |
Klaus D. Beyer, Dominic J. Schepis |
2003-08-05 |
| 6566198 |
CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture |
Heemyong Park, Fariborz Assaderaghi, Ghavam G. Shahidi |
2003-05-20 |
| 6566210 |
Method of improving gate activation by employing atomic oxygen enhanced oxidation |
Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov |
2003-05-20 |
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Method of integrating substrate contact on SOI wafers with STI process |
Effendi Leobandung, Werner Rausch, Dominic J. Schepis, Ghavam G. Shahidi |
2003-02-18 |
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Method for forming notch gate having self-aligned raised source/drain structure |
Ka-Hing Fung, Victor Ku, Dominic J. Schepis |
2003-01-14 |
| 6503833 |
Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby |
Cyril Cabral, Jr., Roy A. Carruthers, Kevin K. Chan, Guy M. Cohen, Paul Kozlowski +3 more |
2003-01-07 |
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Surface engineering to prevent EPI growth on gate poly during selective EPI processing |
Dominic J. Schepis, Michael D. Steigerwalt |
2002-08-27 |
| 6437377 |
Low dielectric constant sidewall spacer using notch gate process |
Ka-Hing Fung, Victor Ku, Dominic J. Schepis |
2002-08-20 |
| 6255145 |
Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting product |
Devendra K. Sadana, Dominic J. Schepis |
2001-07-03 |
| 6057220 |
Titanium polycide stabilization with a porous barrier |
Christine Dehm, Anthony G. Domenicucci, George G. Gifford, Stephen K. Loh, Christopher C. Parks +1 more |
2000-05-02 |
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Low temperature BPSG deposition process |
Jeffrey P. Gambino, Son V. Nguyen |
2000-01-11 |
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Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures |
Herbert L. Ho, Erwin Hammerl, David M. Dobuzinsky, Herbert Palm, Stephen G. Fugardi +2 more |
1998-05-05 |
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Application of thin crystalline Si.sub.3 N.sub.4 liners in shallow trench isolation (STI) structures |
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1997-07-01 |
