Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7960790 | Self-aligned planar double-gate transistor structure | Omer H. Dokumaci, Bruce B. Doris, Kathryn Guarini, Suryanararyan G. Hegde, Meikei Ieong | 2011-06-14 |
| 7741165 | Polycrystalline SiGe Junctions for advanced devices | Kevin K. Chan, Robert J. Miller, Atul Ajmera | 2010-06-22 |
| 7713837 | Low temperature fusion bonding with high surface energy using a wet chemical treatment | Kevin K. Chan, Kathryn Guarini, Antonio F. Saavedra, Jr., Leathen Shi, Dinkar Singh | 2010-05-11 |
| 7566631 | Low temperature fusion bonding with high surface energy using a wet chemical treatment | Kevin K. Chan, Kathryn Guarini, Antonio F. Saavedra, Jr., Leathen Shi, Dinkar Singh | 2009-07-28 |
| 7453123 | Self-aligned planar double-gate transistor structure | Omer H. Dokumaci, Bruce B. Doris, Kathryn Guarini, Suryanarayan G. Hegde, Meikei Ieong | 2008-11-18 |
| 7387924 | Polycrystalline SiGe junctions for advanced devices | Kevin K. Chan, Robert J. Miller, Atul Ajmera | 2008-06-17 |
| 7361556 | Method of fabricating semiconductor side wall fin | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Rama Divakaruni, Edward J. Nowak +1 more | 2008-04-22 |
| 7265417 | Method of fabricating semiconductor side wall fin | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Rama Divakaruni, Edward J. Nowak +1 more | 2007-09-04 |
| 7205185 | Self-aligned planar double-gate process by self-aligned oxidation | Omer H. Dokumaci, Bruce B. Doris, Kathryn Guarini, Suryanarayan G. Hegde, Meikei Ieong | 2007-04-17 |
| 7166521 | SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer | Diane C. Boyd, Hussein I. Hanafi, Dominic J. Schepis, Leathen Shi | 2007-01-23 |
| 7163864 | Method of fabricating semiconductor side wall fin | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Rama Divakaruni, Edward J. Nowak +1 more | 2007-01-16 |
| 7135391 | Polycrystalline SiGe junctions for advanced devices | Kevin K. Chan, Rober J. Miller, Atul Ajmera | 2006-11-14 |
| 7112845 | Double gate trench transistor | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Rama Divakaruni, Jed H. Rankin | 2006-09-26 |
| 6835633 | SOI wafers with 30-100 å buried oxide (BOX) created by wafer bonding using 30-100 å thin oxide as bonding layer | Diane C. Boyd, Hussein I. Hanafi, Dominic J. Schepis, Leathen Shi | 2004-12-28 |
| 6833569 | Self-aligned planar double-gate process by amorphization | Omer H. Dokumaci, Bruce B. Doris, Suryanarayan G. Hegde, Meikei Ieong | 2004-12-21 |
| 6797553 | Method for making multiple threshold voltage FET using multiple work-function gate materials | James W. Adkisson, Arne Ballantine, Ramachandra Divakaruni, Jeffrey B. Johnson, Hon-Sum Philip Wong | 2004-09-28 |
| 6762101 | Damascene double-gate FET | Kevin K. Chan, Paul M. Solomon, Hon-Sum Philip Wong | 2004-07-13 |
| 6686630 | Damascene double-gate MOSFET structure and its fabrication method | Hussein I. Hanafi, Cheruvu Murthy, Philip J. Oldiges, Leathen Shi | 2004-02-03 |
| 6579614 | Structure having refractory metal film on a substrate | Kevin K. Chan, Fenton R. McFeely, Paul M. Solomon, John J. Yurkas | 2003-06-17 |
| 6580132 | Damascene double-gate FET | Kevin K. Chan, Paul M. Solomon, Hon-Sum Philip Wong | 2003-06-17 |
| 6472258 | Double gate trench transistor | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Rama Divakaruni, Jed H. Rankin | 2002-10-29 |
| 6448590 | Multiple threshold voltage FET using multiple work-function gate materials | James W. Adkisson, Arne Ballantine, Ramachandra Divakaruni, Jeffrey B. Johnson, Hon-Sum Philip Wong | 2002-09-10 |
| 6406962 | Vertical trench-formed dual-gate FET device structure and method for creation | Paul D. Agnello, Arne Ballantine, Ramachandra Divakaruni, Edward J. Nowak, Jed H. Rankin | 2002-06-18 |
| 6339002 | Method utilizing CMP to fabricate double gate MOSFETS with conductive sidewall contacts | Kevin K. Chan, Paul M. Solomon | 2002-01-15 |
| 6333247 | Two-step MOSFET gate formation for high-density devices | Kevin K. Chan, Paul M. Solomon | 2001-12-25 |