Issued Patents All Time
Showing 25 most recent of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11177285 | Conductive contacts in semiconductor on insulator substrate | Kangguo Cheng | 2021-11-16 |
| 10734410 | Conductive contacts in semiconductor on insulator substrate | Kangguo Cheng | 2020-08-04 |
| 9685535 | Conductive contacts in semiconductor on insulator substrate | Kangguo Cheng | 2017-06-20 |
| 9673222 | Fin isolation structures facilitating different fin isolation schemes | Ajey Poovannummoottil Jacob, Kangguo Cheng, Bruce B. Doris, Nicolas Loubet, Prasanna Khare | 2017-06-06 |
| 7615457 | Method of fabricating self-aligned bipolar transistor having tapered collector | Hiroyuki Akatsu, Gregory G. Freeman, David R. Greenberg, Marwan H. Khater, William R. Tonti | 2009-11-10 |
| 7566599 | High performance FET with elevated source/drain region | Louis C. Hsu, Rajiv V. Joshi, Carl Radens | 2009-07-28 |
| 7462547 | Method of fabricating a bipolar transistor having reduced collector-base capacitance | Hiroyuki Akatsu, Marwan H. Khater, Christopher M. Schnabel, William R. Tonti | 2008-12-09 |
| 7425754 | Structure and method of self-aligned bipolar transistor having tapered collector | Hiroyuki Akatsu, Gregory G. Freeman, David R. Greenberg, Marwan H. Khater, William R. Tonti | 2008-09-16 |
| 7361556 | Method of fabricating semiconductor side wall fin | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Erin C. Jones, Edward J. Nowak +1 more | 2008-04-22 |
| 7265417 | Method of fabricating semiconductor side wall fin | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Erin C. Jones, Edward J. Nowak +1 more | 2007-09-04 |
| 7190046 | Bipolar transistor having reduced collector-base capacitance | Hiroyuki Akatsu, Marwan H. Khater, Christopher M. Schnabel, William R. Tonti | 2007-03-13 |
| 7170126 | Structure of vertical strained silicon devices | Kangguo Cheng, Dureseti Chidambarrao, Oleg Gluschenkov | 2007-01-30 |
| 7163864 | Method of fabricating semiconductor side wall fin | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Erin C. Jones, Edward J. Nowak +1 more | 2007-01-16 |
| 7112845 | Double gate trench transistor | James W. Adkisson, Paul D. Agnello, Arne Ballantine, Erin C. Jones, Jed H. Rankin | 2006-09-26 |
| 7030481 | High density chip carrier with integrated passive devices | Michael P. Chudzik, Robert H. Dennard, Bruce K. Furman, Rajarao Jammy, Chandrasekhar Narayan +3 more | 2006-04-18 |
| 6998666 | Nitrided STI liner oxide for reduced corner device impact on vertical device performance | Jochen Beintner, Rajarao Jammy | 2006-02-14 |
| 6967137 | Forming collar structures in deep trench capacitors with thermally stable filler material | Michael P. Belyansky, Jack A. Mandelman, Dae-Gyu Park | 2005-11-22 |
| 6964892 | N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same | Lawrence A. Clevenger, Louis L. Hsu, Yujun Li | 2005-11-15 |
| 6962872 | High density chip carrier with integrated passive devices | Michael P. Chudzik, Robert H. Dennard, Bruce K. Furman, Rajarao Jammy, Chandrasekhar Narayan +3 more | 2005-11-08 |
| 6960514 | Pitcher-shaped active area for field effect transistor and method of forming same | Jochen Beintner, Johnathan E. Faltermeier, Philip L. Flaitz, Oleg Gluschenkov, Carol J. Heenan +5 more | 2005-11-01 |
| 6940149 | Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base | Gregory G. Freeman, Marwan H. Khater, William R. Tonti | 2005-09-06 |
| 6897107 | Method for forming TTO nitride liner for improved collar protection and TTO reliability | Thomas W. Dyer, Rajeev Malik, Jack A. Mandelman, Venkatachajam C. Jaiprakash | 2005-05-24 |
| 6890815 | Reduced cap layer erosion for borderless contacts | Johnathan E. Faltermeier, Jeremy K. Stephens, David M. Dobuzinsky, Larry Clevenger, Munir D. Naeem +3 more | 2005-05-10 |
| 6870211 | Self-aligned array contact for memory cells | Johnathan E. Faltermeier, Michael Maldei, Jay William Strane | 2005-03-22 |
| 6869860 | Filling high aspect ratio isolation structures with polysilazane based material | Michael P. Belyansky, Laertis Economikos, Rajarao Jammy, Kenneth Settlemeyer, Padraic Shafer | 2005-03-22 |